Workload Partitioning Strategy for Improved Parallelism on FPGA-CPU Heterogeneous Chips

Sam Amiri; Mohammad Hosseinabady; Andrés Rodríguez; Rafael Asenjo; Angeles Navarro; Jose Nunez-Yanez

doi:10.1109/FPL.2018.00071

Workload Partitioning Strategy for Improved Parallelism on FPGA-CPU Heterogeneous Chips

Sam Amiri
, Mohammad Hosseinabady
, Andrés Rodríguez
, Rafael Asenjo
, Angeles Navarro
, Jose Nunez-Yanez

University of Bristol
Universidad de Malaga

Research output: Chapter in Book/Report/Conference proceeding › Conference proceeding › peer-review

10 Citations (Scopus)

202 Downloads (Pure)

Abstract

In heterogeneous computing, efficient parallelism can be obtained if every device runs the same task on a different portion of the data set. This requires designing a scheduler which assigns data chunks to compute units proportional to their throughputs. For FPGA-CPU heterogeneous devices, to provide the best possible overall throughput, a scheduler should accurately evaluate the different performance behaviour of the compute devices. In this article, we propose a scheduler which initially detects the highest throughput each device can obtain for a specific application with negligible overhead and then partitions the dataset for improved performance. To demonstrate the efficiency of this method, we choose a Zynq UltraScale+ ZCU102 device as the hardware target and parallelise four applications showing that the developed scheduler can provide up to 94.06% of the throughput achievable at an ideal condition, with comparable power and energy consumption.

Original language	English
Title of host publication	28th International Conference on Field Programmable Logic and Applications (FPL)
Publisher	IEEE
Pages	376-380
Number of pages	5
ISBN (Electronic)	978-1-5386-8517-4
ISBN (Print)	978-1-5386-8518-1
DOIs	https://doi.org/10.1109/FPL.2018.00071
Publication status	Published - Aug 2018
Event	28th International Conference on Field Programmable Logic and Applications - Dublin, Ireland Duration: 27 Aug 2018 → 31 Aug 2018 Conference number: 28 https://fpl2018.org/

Publication series

Name	Conference on Field Programmable Logic and Applications
ISSN (Print)	1946-147X
ISSN (Electronic)	1946-1488

Conference

Conference	28th International Conference on Field Programmable Logic and Applications
Abbreviated title	FPL
Country/Territory	Ireland
City	Dublin
Period	27/08/18 → 31/08/18
Internet address	https://fpl2018.org/

Bibliographical note

© 2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Keywords

scheduling
heterogeneous
parallelisation
throughput
energy
power
FPGA
ARM
SoC
ZCU102

Access to Document

10.1109/FPL.2018.00071

Post-PrintAccepted author manuscript, 775 KBLicence: CC BY

Cite this

Amiri, S., Hosseinabady, M., Rodríguez, A., Asenjo, R., Navarro, A., & Nunez-Yanez, J. (2018). Workload Partitioning Strategy for Improved Parallelism on FPGA-CPU Heterogeneous Chips. In 28th International Conference on Field Programmable Logic and Applications (FPL) (pp. 376-380). (Conference on Field Programmable Logic and Applications ). IEEE. https://doi.org/10.1109/FPL.2018.00071

Workload Partitioning Strategy for Improved Parallelism on FPGA-CPU Heterogeneous Chips. / Amiri, Sam; Hosseinabady, Mohammad; Rodríguez, Andrés et al.
28th International Conference on Field Programmable Logic and Applications (FPL). IEEE, 2018. p. 376-380 (Conference on Field Programmable Logic and Applications ).

Research output: Chapter in Book/Report/Conference proceeding › Conference proceeding › peer-review

Amiri, S, Hosseinabady, M, Rodríguez, A, Asenjo, R, Navarro, A & Nunez-Yanez, J 2018, Workload Partitioning Strategy for Improved Parallelism on FPGA-CPU Heterogeneous Chips. in 28th International Conference on Field Programmable Logic and Applications (FPL). Conference on Field Programmable Logic and Applications , IEEE, pp. 376-380, 28th International Conference on Field Programmable Logic and Applications , Dublin, Ireland, 27/08/18. https://doi.org/10.1109/FPL.2018.00071

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Workload Partitioning Strategy for Improved Parallelism on FPGA-CPU Heterogeneous Chips

Abstract

Publication series

Conference

Bibliographical note

UN SDGs

Keywords

Access to Document

Fingerprint

Cite this