Workload Partitioning Strategy for Improved Parallelism on FPGA-CPU Heterogeneous Chips

Sam Amiri; Mohammad Hosseinabady; Andrés Rodríguez; Rafael Asenjo; Angeles Navarro; Jose Nunez-Yanez

doi:10.1109/FPL.2018.00071

Workload Partitioning Strategy for Improved Parallelism on FPGA-CPU Heterogeneous Chips

Sam Amiri, Mohammad Hosseinabady, Andrés Rodríguez, Rafael Asenjo, Angeles Navarro, Jose Nunez-Yanez

Research output: Chapter in Book/Report/Conference proceeding › Conference proceeding › peer-review

9 Citations (Scopus)

90 Downloads (Pure)

Abstract

In heterogeneous computing, efficient parallelism can be obtained if every device runs the same task on a different portion of the data set. This requires designing a scheduler which assigns data chunks to compute units proportional to their throughputs. For FPGA-CPU heterogeneous devices, to provide the best possible overall throughput, a scheduler should accurately evaluate the different performance behaviour of the compute devices. In this article, we propose a scheduler which initially detects the highest throughput each device can obtain for a specific application with negligible overhead and then partitions the dataset for improved performance. To demonstrate the efficiency of this method, we choose a Zynq UltraScale+ ZCU102 device as the hardware target and parallelise four applications showing that the developed scheduler can provide up to 94.06% of the throughput achievable at an ideal condition, with comparable power and energy consumption.

Original language	English
Title of host publication	28th International Conference on Field Programmable Logic and Applications (FPL)
Publisher	IEEE
Pages	376-380
Number of pages	5
ISBN (Electronic)	978-1-5386-8517-4
ISBN (Print)	978-1-5386-8518-1
DOIs	https://doi.org/10.1109/FPL.2018.00071
Publication status	Published - Aug 2018
Event	28th International Conference on Field Programmable Logic and Applications - Dublin, Ireland Duration: 27 Aug 2018 → 31 Aug 2018 Conference number: 28 https://fpl2018.org/

Publication series

Name	Conference on Field Programmable Logic and Applications
ISSN (Print)	1946-147X
ISSN (Electronic)	1946-1488

Conference

Conference	28th International Conference on Field Programmable Logic and Applications
Abbreviated title	FPL
Country/Territory	Ireland
City	Dublin
Period	27/08/18 → 31/08/18
Internet address	https://fpl2018.org/

Bibliographical note

© 2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.

Keywords

scheduling
heterogeneous
parallelisation
throughput
energy
power
FPGA
ARM
SoC
ZCU102

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1109/FPL.2018.00071

Post-PrintAccepted author manuscript, 775 KBLicence: CC BY

Cite this

Amiri, S., Hosseinabady, M., Rodríguez, A., Asenjo, R., Navarro, A., & Nunez-Yanez, J. (2018). Workload Partitioning Strategy for Improved Parallelism on FPGA-CPU Heterogeneous Chips. In 28th International Conference on Field Programmable Logic and Applications (FPL) (pp. 376-380). (Conference on Field Programmable Logic and Applications ). IEEE. https://doi.org/10.1109/FPL.2018.00071

Workload Partitioning Strategy for Improved Parallelism on FPGA-CPU Heterogeneous Chips. / Amiri, Sam; Hosseinabady, Mohammad; Rodríguez, Andrés et al.
28th International Conference on Field Programmable Logic and Applications (FPL). IEEE, 2018. p. 376-380 (Conference on Field Programmable Logic and Applications ).

Research output: Chapter in Book/Report/Conference proceeding › Conference proceeding › peer-review

Amiri, S, Hosseinabady, M, Rodríguez, A, Asenjo, R, Navarro, A & Nunez-Yanez, J 2018, Workload Partitioning Strategy for Improved Parallelism on FPGA-CPU Heterogeneous Chips. in 28th International Conference on Field Programmable Logic and Applications (FPL). Conference on Field Programmable Logic and Applications , IEEE, pp. 376-380, 28th International Conference on Field Programmable Logic and Applications , Dublin, Ireland, 27/08/18. https://doi.org/10.1109/FPL.2018.00071

@inproceedings{4ad9c85b37ad4bd0baddb61572fe2a1e,

title = "Workload Partitioning Strategy for Improved Parallelism on FPGA-CPU Heterogeneous Chips",

abstract = "In heterogeneous computing, efficient parallelism can be obtained if every device runs the same task on a different portion of the data set. This requires designing a scheduler which assigns data chunks to compute units proportional to their throughputs. For FPGA-CPU heterogeneous devices, to provide the best possible overall throughput, a scheduler should accurately evaluate the different performance behaviour of the compute devices. In this article, we propose a scheduler which initially detects the highest throughput each device can obtain for a specific application with negligible overhead and then partitions the dataset for improved performance. To demonstrate the efficiency of this method, we choose a Zynq UltraScale+ ZCU102 device as the hardware target and parallelise four applications showing that the developed scheduler can provide up to 94.06% of the throughput achievable at an ideal condition, with comparable power and energy consumption.",

keywords = "scheduling, heterogeneous, parallelisation, throughput, energy, power, FPGA, ARM, SoC, ZCU102",

author = "Sam Amiri and Mohammad Hosseinabady and Andr{\'e}s Rodr{\'i}guez and Rafael Asenjo and Angeles Navarro and Jose Nunez-Yanez",

note = "{\textcopyright} 2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. ; 28th International Conference on Field Programmable Logic and Applications , FPL ; Conference date: 27-08-2018 Through 31-08-2018",

year = "2018",

month = aug,

doi = "10.1109/FPL.2018.00071",

language = "English",

isbn = "978-1-5386-8518-1",

series = "Conference on Field Programmable Logic and Applications ",

publisher = "IEEE",

pages = "376--380",

booktitle = "28th International Conference on Field Programmable Logic and Applications (FPL)",

address = "United States",

url = "https://fpl2018.org/",

}

TY - GEN

T1 - Workload Partitioning Strategy for Improved Parallelism on FPGA-CPU Heterogeneous Chips

AU - Amiri, Sam

AU - Hosseinabady, Mohammad

AU - Rodríguez, Andrés

AU - Asenjo, Rafael

AU - Navarro, Angeles

AU - Nunez-Yanez, Jose

N1 - Conference code: 28

PY - 2018/8

Y1 - 2018/8

N2 - In heterogeneous computing, efficient parallelism can be obtained if every device runs the same task on a different portion of the data set. This requires designing a scheduler which assigns data chunks to compute units proportional to their throughputs. For FPGA-CPU heterogeneous devices, to provide the best possible overall throughput, a scheduler should accurately evaluate the different performance behaviour of the compute devices. In this article, we propose a scheduler which initially detects the highest throughput each device can obtain for a specific application with negligible overhead and then partitions the dataset for improved performance. To demonstrate the efficiency of this method, we choose a Zynq UltraScale+ ZCU102 device as the hardware target and parallelise four applications showing that the developed scheduler can provide up to 94.06% of the throughput achievable at an ideal condition, with comparable power and energy consumption.

AB - In heterogeneous computing, efficient parallelism can be obtained if every device runs the same task on a different portion of the data set. This requires designing a scheduler which assigns data chunks to compute units proportional to their throughputs. For FPGA-CPU heterogeneous devices, to provide the best possible overall throughput, a scheduler should accurately evaluate the different performance behaviour of the compute devices. In this article, we propose a scheduler which initially detects the highest throughput each device can obtain for a specific application with negligible overhead and then partitions the dataset for improved performance. To demonstrate the efficiency of this method, we choose a Zynq UltraScale+ ZCU102 device as the hardware target and parallelise four applications showing that the developed scheduler can provide up to 94.06% of the throughput achievable at an ideal condition, with comparable power and energy consumption.

KW - scheduling

KW - heterogeneous

KW - parallelisation

KW - throughput

KW - energy

KW - power

KW - FPGA

KW - ARM

KW - SoC

KW - ZCU102

U2 - 10.1109/FPL.2018.00071

DO - 10.1109/FPL.2018.00071

M3 - Conference proceeding

SN - 978-1-5386-8518-1

T3 - Conference on Field Programmable Logic and Applications

SP - 376

EP - 380

BT - 28th International Conference on Field Programmable Logic and Applications (FPL)

PB - IEEE

T2 - 28th International Conference on Field Programmable Logic and Applications

Y2 - 27 August 2018 through 31 August 2018

ER -

Workload Partitioning Strategy for Improved Parallelism on FPGA-CPU Heterogeneous Chips

Abstract

Publication series

Conference

Bibliographical note

Keywords

UN SDGs

Access to Document

Fingerprint

Cite this