Workload Partitioning Strategy for Improved Parallelism on FPGA-CPU Heterogeneous Chips

Sam Amiri, Mohammad Hosseinabady, Andrés Rodríguez, Rafael Asenjo, Angeles Navarro, Jose Nunez-Yanez

Research output: Chapter in Book/Report/Conference proceedingConference proceeding

2 Citations (Scopus)
11 Downloads (Pure)

Abstract

In heterogeneous computing, efficient parallelism can be obtained if every device runs the same task on a different portion of the data set. This requires designing a scheduler which assigns data chunks to compute units proportional to their throughputs. For FPGA-CPU heterogeneous devices, to provide the best possible overall throughput, a scheduler should accurately evaluate the different performance behaviour of the compute devices. In this article, we propose a scheduler which initially detects the highest throughput each device can obtain for a specific application with negligible overhead and then partitions the dataset for improved performance. To demonstrate the efficiency of this method, we choose a Zynq UltraScale+ ZCU102 device as the hardware target and parallelise four applications showing that the developed scheduler can provide up to 94.06% of the throughput achievable at an ideal condition, with comparable power and energy consumption.
Original languageEnglish
Title of host publication28th International Conference on Field Programmable Logic and Applications (FPL)
PublisherIEEE
Pages376-380
Number of pages5
ISBN (Electronic)978-1-5386-8517-4
ISBN (Print)978-1-5386-8518-1
DOIs
Publication statusPublished - Aug 2018
Event28th International Conference on Field Programmable Logic and Applications - Dublin, Ireland
Duration: 27 Aug 201831 Aug 2018
Conference number: 28
https://fpl2018.org/

Publication series

NameConference on Field Programmable Logic and Applications
ISSN (Print)1946-147X
ISSN (Electronic)1946-1488

Conference

Conference28th International Conference on Field Programmable Logic and Applications
Abbreviated titleFPL
CountryIreland
CityDublin
Period27/08/1831/08/18
Internet address

Bibliographical note

© 2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.

Keywords

  • scheduling
  • heterogeneous
  • parallelisation
  • throughput
  • energy
  • power
  • FPGA
  • ARM
  • SoC
  • ZCU102

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  • Cite this

    Amiri, S., Hosseinabady, M., Rodríguez, A., Asenjo, R., Navarro, A., & Nunez-Yanez, J. (2018). Workload Partitioning Strategy for Improved Parallelism on FPGA-CPU Heterogeneous Chips. In 28th International Conference on Field Programmable Logic and Applications (FPL) (pp. 376-380). (Conference on Field Programmable Logic and Applications ). IEEE. https://doi.org/10.1109/FPL.2018.00071