The Stripe Fortified GCT: A new GCT design for maximizing the controllable current

Neophytos Lophitis, M. Antoniou, F. Udrea, I. Nistor, T. Wikstrom, J. Vobecky, M. Rahimo

    Research output: Chapter in Book/Report/Conference proceedingConference proceeding

    5 Citations (Scopus)
    58 Downloads (Pure)

    Abstract

    In this paper we introduce a new GCT design, namely the Stripe Fortified GCT, for the purpose of maximizing the controllable current by optimizing the current flow path in the device during turn-off. The main design of the new device along with variants are introduced. The MCC performance of this novel structure is assessed with a developed two dimensional model for full wafer simulations. Our results show that this new design is a very good candidate for increasing the MCC to values more than 5000A.

    Publisher Statement: © 2014 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
    Original languageEnglish
    Title of host publication2014 IEEE 26th International Symposium on Power Semiconductor Devices & IC's (ISPSD)
    PublisherIEEE
    Pages123 - 126
    Number of pages4
    ISBN (Electronic)978-1-4799-2918-4, 978-1-4799-2916-0
    ISBN (Print)978-1-4799-2917-7
    DOIs
    Publication statusPublished - 2014
    EventIEEE International Symposium on Power Semiconductor Devices and ICs - Waikoloa Village, United States
    Duration: 15 Jun 201419 Jun 2014

    Conference

    ConferenceIEEE International Symposium on Power Semiconductor Devices and ICs
    Abbreviated titleISPSD
    Country/TerritoryUnited States
    CityWaikoloa Village
    Period15/06/1419/06/14

    Bibliographical note

    © 2014 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.

    Keywords

    • Cathodes
    • Controllability
    • Current density
    • Junctions
    • Logic gates
    • Semiconductor device modeling
    • Thyristors
    • 2D model
    • GCT design
    • MCC performance
    • current flow path
    • gate commutated thyristors
    • maximum controllable current
    • stripe fortified GCT
    • semiconductor device models
    • thyristors

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