Abstract
This study presents energy and area-efficient hardware architectures to map fully parallel cortical columns on reconfigurable platform - field programmable gate arrays (FPGAs). An area-efficient architecture is proposed at the system level and benchmarked with a speech recognition application. Owing to the spatio-temporal nature of spiking neurons it is more suitable to map such architectures on FPGAs where signals can be represented in binary form and communication can be performed through the use of spikes. The viability of implementing multiple recurrent neural reservoirs is demonstrated with a novel multiplier-less reconfigurable architectures and a design strategy is devised for its implementation.
| Original language | English |
|---|---|
| Pages (from-to) | 432-440 |
| Number of pages | 9 |
| Journal | IET Science, Measurement and Technology |
| Volume | 8 |
| Issue number | 6 |
| DOIs | |
| Publication status | Published - 1 Nov 2014 |
| Externally published | Yes |
Bibliographical note
© 2014 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.Keywords
- speech recognition
- field programmable gate arrays
- neurophysiology
- reconfigurable architectures
- recurrent neural nets
- fully parallel energy efficient cortical columns
- multiplier-less reconfigurable architectures
- multiple recurrent neural reservoirs
- spiking neurons
- speech recognition application
- FPGAs
- reconfigurable platform
- area-efficient hardware architectures
ASJC Scopus subject areas
- Atomic and Molecular Physics, and Optics
- Electrical and Electronic Engineering