Simultaneous multiprocessing in a software-defined heterogeneous FPGA

Jose Nunez-Yanez, Sam Amiri, Mohammad Hosseinabady, Andrés Rodríguez, Rafael Asenjo, Angeles Navarro, Dario Suarez, Ruben Gran

Research output: Contribution to journalArticle

6 Citations (Scopus)
7 Downloads (Pure)

Abstract

Heterogeneous chips that combine CPUs and FPGAs can distribute processing so that the algorithm tasks are mapped onto the most suitable processing element. New software-defined high-level design environments for these chips use general purpose languages such as C++ and OpenCL for hardware and interface generation without the need for register transfer language expertise. These advances in hardware compilers have resulted in significant increases in FPGA design productivity. In this paper, we investigate how to enhance an existing software-defined framework to reduce overheads and enable the utilization of all the available CPU cores in parallel with the FPGA hardware accelerators. Instead of selecting the best processing element for a task and simply offloading onto it, we introduce two schedulers, Dynamic and LogFit, which distribute the tasks among all the resources in an optimal manner. A new platform is created based on interrupts that removes spin-locks and allows the processing cores to sleep when not performing useful work. For a compute-intensive application, we obtained up to 45.56% more throughput and 17.89% less energy consumption when all devices of a Zynq-7000 SoC collaborate in the computation compared against FPGA-only execution.
Original languageEnglish
Pages (from-to)4078–4095
Number of pages18
JournalThe Journal of Supercomputing
Volume75
Issue number8
Early online date16 Apr 2018
DOIs
Publication statusPublished - Aug 2019

Fingerprint

Field programmable gate arrays (FPGA)
Processing
Program processors
Hardware
Computer hardware
Particle accelerators
Energy utilization
Productivity
Throughput

Bibliographical note

This article is distributed under the terms of the Creative Commons Attribution 4.0 International License (http://creativecommons.org/licenses/by/4.0/), which permits unrestricted use, distribution, and reproduction in any medium, provided you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license, and indicate if changes were made.

Keywords

  • Dynamic scheduler
  • Energy reduction
  • FPGAs
  • Heterogeneous
  • Interrupts
  • LogFit scheduler
  • Performance improvement

ASJC Scopus subject areas

  • Software
  • Theoretical Computer Science
  • Information Systems
  • Hardware and Architecture

Cite this

Nunez-Yanez, J., Amiri, S., Hosseinabady, M., Rodríguez, A., Asenjo, R., Navarro, A., ... Gran, R. (2019). Simultaneous multiprocessing in a software-defined heterogeneous FPGA. The Journal of Supercomputing, 75(8), 4078–4095. https://doi.org/10.1007/s11227-018-2367-9

Simultaneous multiprocessing in a software-defined heterogeneous FPGA. / Nunez-Yanez, Jose; Amiri, Sam; Hosseinabady, Mohammad; Rodríguez, Andrés; Asenjo, Rafael; Navarro, Angeles; Suarez, Dario; Gran, Ruben.

In: The Journal of Supercomputing, Vol. 75, No. 8, 08.2019, p. 4078–4095.

Research output: Contribution to journalArticle

Nunez-Yanez, J, Amiri, S, Hosseinabady, M, Rodríguez, A, Asenjo, R, Navarro, A, Suarez, D & Gran, R 2019, 'Simultaneous multiprocessing in a software-defined heterogeneous FPGA' The Journal of Supercomputing, vol. 75, no. 8, pp. 4078–4095. https://doi.org/10.1007/s11227-018-2367-9
Nunez-Yanez J, Amiri S, Hosseinabady M, Rodríguez A, Asenjo R, Navarro A et al. Simultaneous multiprocessing in a software-defined heterogeneous FPGA. The Journal of Supercomputing. 2019 Aug;75(8):4078–4095. https://doi.org/10.1007/s11227-018-2367-9
Nunez-Yanez, Jose ; Amiri, Sam ; Hosseinabady, Mohammad ; Rodríguez, Andrés ; Asenjo, Rafael ; Navarro, Angeles ; Suarez, Dario ; Gran, Ruben. / Simultaneous multiprocessing in a software-defined heterogeneous FPGA. In: The Journal of Supercomputing. 2019 ; Vol. 75, No. 8. pp. 4078–4095.
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