Simultaneous multiprocessing in a software-defined heterogeneous FPGA

Jose Nunez-Yanez, Sam Amiri, Mohammad Hosseinabady, Andrés Rodríguez, Rafael Asenjo, Angeles Navarro, Dario Suarez, Ruben Gran

    Research output: Contribution to journalArticlepeer-review

    9 Citations (Scopus)
    59 Downloads (Pure)


    Heterogeneous chips that combine CPUs and FPGAs can distribute processing so that the algorithm tasks are mapped onto the most suitable processing element. New software-defined high-level design environments for these chips use general purpose languages such as C++ and OpenCL for hardware and interface generation without the need for register transfer language expertise. These advances in hardware compilers have resulted in significant increases in FPGA design productivity. In this paper, we investigate how to enhance an existing software-defined framework to reduce overheads and enable the utilization of all the available CPU cores in parallel with the FPGA hardware accelerators. Instead of selecting the best processing element for a task and simply offloading onto it, we introduce two schedulers, Dynamic and LogFit, which distribute the tasks among all the resources in an optimal manner. A new platform is created based on interrupts that removes spin-locks and allows the processing cores to sleep when not performing useful work. For a compute-intensive application, we obtained up to 45.56% more throughput and 17.89% less energy consumption when all devices of a Zynq-7000 SoC collaborate in the computation compared against FPGA-only execution.
    Original languageEnglish
    Pages (from-to)4078–4095
    Number of pages18
    JournalThe Journal of Supercomputing
    Issue number8
    Early online date16 Apr 2018
    Publication statusPublished - Aug 2019

    Bibliographical note

    This article is distributed under the terms of the Creative Commons Attribution 4.0 International License (, which permits unrestricted use, distribution, and reproduction in any medium, provided you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license, and indicate if changes were made.


    • Dynamic scheduler
    • Energy reduction
    • FPGAs
    • Heterogeneous
    • Interrupts
    • LogFit scheduler
    • Performance improvement

    ASJC Scopus subject areas

    • Software
    • Theoretical Computer Science
    • Information Systems
    • Hardware and Architecture


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