Abstract
| Language | English |
|---|---|
| Article number | 1000172 |
| Number of pages | 10 |
| Journal | Journal of Electrical Engineering and Electronic Technology |
| Volume | 8 |
| Issue number | 1 |
| DOIs | |
| Publication status | Published - 31 Jan 2019 |
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Keywords
- Phase Locked Loop
- Phase Margin
- Phase noise
- Lock time
- Jitter variance
- Damping Coefficient
- VCO sensitivity
Cite this
Relationship between Jitter variance, Lock time and Phase noise of a second-order PLL. / Vershinin, Yuri; Mazumdar, Dipayan ; Kadambi, Govind.
In: Journal of Electrical Engineering and Electronic Technology, Vol. 8, No. 1, 1000172, 31.01.2019.Research output: Contribution to journal › Article
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TY - JOUR
T1 - Relationship between Jitter variance, Lock time and Phase noise of a second-order PLL.
AU - Vershinin, Yuri
AU - Mazumdar, Dipayan
AU - Kadambi, Govind
PY - 2019/1/31
Y1 - 2019/1/31
N2 - This paper covers analytical relationships between phase noise, lock time and jitter variance. An expression is derived for Lock time in terms phase margin. Analytical expressions have been derived in this paper for the variation of Lock time with respect to Phase Margin and lock time with respect to its damping coefficient.
AB - This paper covers analytical relationships between phase noise, lock time and jitter variance. An expression is derived for Lock time in terms phase margin. Analytical expressions have been derived in this paper for the variation of Lock time with respect to Phase Margin and lock time with respect to its damping coefficient.
KW - Phase Locked Loop
KW - Phase Margin
KW - Phase noise
KW - Lock time
KW - Jitter variance
KW - Damping Coefficient
KW - VCO sensitivity
U2 - 10.4172/2325-9833.1000172
DO - 10.4172/2325-9833.1000172
M3 - Article
VL - 8
JO - Journal of Electrical Engineering and Electronic Technology
T2 - Journal of Electrical Engineering and Electronic Technology
JF - Journal of Electrical Engineering and Electronic Technology
SN - 2325-9833
IS - 1
M1 - 1000172
ER -