Reconfigurable neurons-making the most of configurable logic blocks (CLBs)

Arfan Ghani, Chan H. See, Hassan Migdadi, Rameez Asif, Raed A A Abd-Alhameed, James M. Noras

    Research output: Chapter in Book/Report/Conference proceedingConference proceeding

    1 Citation (Scopus)

    Abstract

    An area-efficient hardware architecture is used to map fully parallel cortical columns on Field Programmable Gate Arrays (FPGA) is presented in this paper. To demonstrate the concept of this work, the proposed architecture is shown at the system level and benchmarked with image and speech recognition applications. Due to the spatio-temporal nature of spiking neurons, this has allowed such architectures to map on FPGAs in which communication can be performed through the use of spikes and signal can be represented in binary form. The process and viability of designing and implementing the multiple recurrent neural reservoirs with a novel multiplier-less reconfigurable architectures is described.

    Original languageEnglish
    Title of host publication2015 Internet Technologies and Applications, ITA 2015 - Proceedings of the 6th International Conference
    PublisherInstitute of Electrical and Electronics Engineers Inc.
    Pages475-478
    Number of pages4
    ISBN (Electronic)9781479980369
    DOIs
    Publication statusPublished - 2 Nov 2015
    Event6th International Conference on Internet Technologies and Applications, ITA 2015 - Wrexham, United Kingdom
    Duration: 8 Sep 201511 Sep 2015

    Conference

    Conference6th International Conference on Internet Technologies and Applications, ITA 2015
    CountryUnited Kingdom
    CityWrexham
    Period8/09/1511/09/15

    Keywords

    • FPGAs
    • neural signal processing
    • reconfigurable computing
    • recurrent neural networks
    • reservior computing

    ASJC Scopus subject areas

    • Computer Science Applications
    • Computer Networks and Communications

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  • Cite this

    Ghani, A., See, C. H., Migdadi, H., Asif, R., Abd-Alhameed, R. A. A., & Noras, J. M. (2015). Reconfigurable neurons-making the most of configurable logic blocks (CLBs). In 2015 Internet Technologies and Applications, ITA 2015 - Proceedings of the 6th International Conference (pp. 475-478). [7317451] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ITechA.2015.7317451