Abstract
An area-efficient hardware architecture is used to map fully parallel cortical columns on Field Programmable Gate Arrays (FPGA) is presented in this paper. To demonstrate the concept of this work, the proposed architecture is shown at the system level and benchmarked with image and speech recognition applications. Due to the spatio-temporal nature of spiking neurons, this has allowed such architectures to map on FPGAs in which communication can be performed through the use of spikes and signal can be represented in binary form. The process and viability of designing and implementing the multiple recurrent neural reservoirs with a novel multiplier-less reconfigurable architectures is described.
Original language | English |
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Title of host publication | 2015 Internet Technologies and Applications, ITA 2015 - Proceedings of the 6th International Conference |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 475-478 |
Number of pages | 4 |
ISBN (Electronic) | 9781479980369 |
DOIs | |
Publication status | Published - 2 Nov 2015 |
Event | 6th International Conference on Internet Technologies and Applications, ITA 2015 - Wrexham, United Kingdom Duration: 8 Sept 2015 → 11 Sept 2015 |
Conference
Conference | 6th International Conference on Internet Technologies and Applications, ITA 2015 |
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Country/Territory | United Kingdom |
City | Wrexham |
Period | 8/09/15 → 11/09/15 |
Keywords
- FPGAs
- neural signal processing
- reconfigurable computing
- recurrent neural networks
- reservior computing
ASJC Scopus subject areas
- Computer Science Applications
- Computer Networks and Communications