Programmable Architectures for Histogram of Oriented Gradients Processing

Colm Kelly, Roger Woods, Moslem Amiri, Fahad Siddiqui, Karen Rafferty

    Research output: Chapter in Book/Report/Conference proceedingChapterpeer-review


    There is an increasing demand for high performance image processing platforms based on field programmable gate array (FPGA). The Histogram of Orientated Gradients (HOG) algorithm is a feature descriptor algorithm used in object detection for many security applications. The chapter examines the implementation of this key algorithm using an FPGA-based soft-core architecture approach. Firstly, the HOG algorithm is described and its performance profiled from a computation and bandwidth perspective. Then the IPPro soft-core processor architecture is introduced and a number of mapping strategies are covered. A HOG implementation is demonstrated on a Zynq platform, resulting in a design operating at 15.36 fps; this compares favorably with the performance and resources of hand-crafted VHDL code.
    Original languageEnglish
    Title of host publicationHandbook of Signal Processing Systems
    EditorsShuvra S. Bhattacharyya, Ed F. Deprettere, Rainer Leupers, Jarmo Takala
    PublisherSpringer International Publishing
    Number of pages34
    ISBN (Electronic)978-3-319-91734-4
    ISBN (Print)978-3-319-91733-7
    Publication statusPublished - 13 Oct 2018

    ASJC Scopus subject areas

    • Engineering(all)
    • Computer Science(all)


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