Performance enhancement defect tolerance in the cell matrix architecture

C. R. Saha; S. J. Bellis; A. Mathewson; E. M. Popovici

doi:10.1109/ICMEL.2004.1314949

Performance enhancement defect tolerance in the cell matrix architecture

C. R. Saha
, S. J. Bellis
, A. Mathewson
, E. M. Popovici

National Microelectronics Research Centre Ireland

Research output: Chapter in Book/Report/Conference proceeding › Conference proceeding › peer-review

3 Citations (Scopus)

Abstract

This research concentrates on the area of fault tolerant circuit implementation in a field programmable type architecture, In particular, an architecture called the Cell Matrix, presented as a fault tolerant alternative to field programmable gate arrays using their Supercell approach, is studied. Architectural constraints to implement fault tolerant circuit design in this architecture are discussed. Some modifications of its basic Structure, such as the integration of circuitry for error correction and scan path, to enhance fault tolerant circuits design are introduced and are compared to the Supercell approach.

Original language	English
Title of host publication	24th International Conference on Microelectronics, 2004
Publisher	IEEE
Pages	777-780
Number of pages	4
Volume	2
ISBN (Print)	0-7803-8166-1
DOIs	https://doi.org/10.1109/ICMEL.2004.1314949
Publication status	Published - 19 Jun 2004
Event	2004 24th International Conference on Microelectronics - Nis, Serbia, Nis, Serbia Duration: 16 May 2004 → 19 May 2004 Conference number: 24

Conference

Conference	2004 24th International Conference on Microelectronics
Abbreviated title	MIEL 2004
Country/Territory	Serbia
City	Nis
Period	16/05/04 → 19/05/04

Keywords

Fault tolerance
Circuit faults
Field programmable gate arrays
Circuit synthesis
Telecommunication computing
Redundancy
Fault tolerant systems
Table lookup
Microelectronics
Circuit testing
integrated circuit design
error correction
fault tolerance
CMOS digital integrated circuits
fault tolerant circuits design
performance enhancement defect tolerance
cell matrix architecture
fault tolerant circuit implementation
field programmable type architecture
Cell Matrix
Supercell approach
architectural constraints
scan path

Access to Document

10.1109/ICMEL.2004.1314949

Cite this

@inproceedings{0b86c3427b4e460d8458faa3a4f85830,

title = "Performance enhancement defect tolerance in the cell matrix architecture",

abstract = " This research concentrates on the area of fault tolerant circuit implementation in a field programmable type architecture, In particular, an architecture called the Cell Matrix, presented as a fault tolerant alternative to field programmable gate arrays using their Supercell approach, is studied. Architectural constraints to implement fault tolerant circuit design in this architecture are discussed. Some modifications of its basic Structure, such as the integration of circuitry for error correction and scan path, to enhance fault tolerant circuits design are introduced and are compared to the Supercell approach.",

keywords = "Fault tolerance, Circuit faults, Field programmable gate arrays, Circuit synthesis, Telecommunication computing, Redundancy, Fault tolerant systems, Table lookup, Microelectronics, Circuit testing, integrated circuit design, error correction, fault tolerance, CMOS digital integrated circuits, fault tolerant circuits design, performance enhancement defect tolerance, cell matrix architecture, fault tolerant circuit implementation, field programmable type architecture, Cell Matrix, Supercell approach, architectural constraints, scan path",

author = "Saha, \{C. R.\} and Bellis, \{S. J.\} and A. Mathewson and Popovici, \{E. M.\}",

year = "2004",

month = jun,

day = "19",

doi = "10.1109/ICMEL.2004.1314949",

language = "English",

isbn = "0-7803-8166-1",

volume = "2",

pages = "777--780",

booktitle = "24th International Conference on Microelectronics, 2004",

publisher = "IEEE",

address = "United States",

note = "2004 24th International Conference on Microelectronics, MIEL 2004 ; Conference date: 16-05-2004 Through 19-05-2004",

}

TY - GEN

T1 - Performance enhancement defect tolerance in the cell matrix architecture

AU - Saha, C. R.

AU - Bellis, S. J.

AU - Mathewson, A.

AU - Popovici, E. M.

N1 - Conference code: 24

PY - 2004/6/19

Y1 - 2004/6/19

N2 - This research concentrates on the area of fault tolerant circuit implementation in a field programmable type architecture, In particular, an architecture called the Cell Matrix, presented as a fault tolerant alternative to field programmable gate arrays using their Supercell approach, is studied. Architectural constraints to implement fault tolerant circuit design in this architecture are discussed. Some modifications of its basic Structure, such as the integration of circuitry for error correction and scan path, to enhance fault tolerant circuits design are introduced and are compared to the Supercell approach.

AB - This research concentrates on the area of fault tolerant circuit implementation in a field programmable type architecture, In particular, an architecture called the Cell Matrix, presented as a fault tolerant alternative to field programmable gate arrays using their Supercell approach, is studied. Architectural constraints to implement fault tolerant circuit design in this architecture are discussed. Some modifications of its basic Structure, such as the integration of circuitry for error correction and scan path, to enhance fault tolerant circuits design are introduced and are compared to the Supercell approach.

KW - Fault tolerance

KW - Circuit faults

KW - Field programmable gate arrays

KW - Circuit synthesis

KW - Telecommunication computing

KW - Redundancy

KW - Fault tolerant systems

KW - Table lookup

KW - Microelectronics

KW - Circuit testing

KW - integrated circuit design

KW - error correction

KW - fault tolerance

KW - CMOS digital integrated circuits

KW - fault tolerant circuits design

KW - performance enhancement defect tolerance

KW - cell matrix architecture

KW - fault tolerant circuit implementation

KW - field programmable type architecture

KW - Cell Matrix

KW - Supercell approach

KW - architectural constraints

KW - scan path

U2 - 10.1109/ICMEL.2004.1314949

DO - 10.1109/ICMEL.2004.1314949

M3 - Conference proceeding

SN - 0-7803-8166-1

VL - 2

SP - 777

EP - 780

BT - 24th International Conference on Microelectronics, 2004

PB - IEEE

T2 - 2004 24th International Conference on Microelectronics

Y2 - 16 May 2004 through 19 May 2004

ER -

Performance enhancement defect tolerance in the cell matrix architecture

Abstract

Conference

Keywords

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