Performance enhancement defect tolerance in the cell matrix architecture

C. R. Saha, S. J. Bellis, A. Mathewson, E. M. Popovici

Research output: Chapter in Book/Report/Conference proceedingConference proceedingpeer-review

3 Citations (Scopus)


This research concentrates on the area of fault tolerant circuit implementation in a field programmable type architecture, In particular, an architecture called the Cell Matrix, presented as a fault tolerant alternative to field programmable gate arrays using their Supercell approach, is studied. Architectural constraints to implement fault tolerant circuit design in this architecture are discussed. Some modifications of its basic Structure, such as the integration of circuitry for error correction and scan path, to enhance fault tolerant circuits design are introduced and are compared to the Supercell approach.
Original languageEnglish
Title of host publication24th International Conference on Microelectronics, 2004
Number of pages4
ISBN (Print)0-7803-8166-1
Publication statusPublished - 19 Jun 2004
Event2004 24th International Conference on Microelectronics - Nis, Serbia, Nis, Serbia
Duration: 16 May 200419 May 2004
Conference number: 24


Conference2004 24th International Conference on Microelectronics
Abbreviated titleMIEL 2004


  • Fault tolerance
  • Circuit faults
  • Field programmable gate arrays
  • Circuit synthesis
  • Telecommunication computing
  • Redundancy
  • Fault tolerant systems
  • Table lookup
  • Microelectronics
  • Circuit testing
  • integrated circuit design
  • error correction
  • fault tolerance
  • CMOS digital integrated circuits
  • fault tolerant circuits design
  • performance enhancement defect tolerance
  • cell matrix architecture
  • fault tolerant circuit implementation
  • field programmable type architecture
  • Cell Matrix
  • Supercell approach
  • architectural constraints
  • scan path


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