Novel reconfigurable hardware implementation of polynomial matrix/vector multiplications

S. Kasap, S. Redif

Research output: Chapter in Book/Report/Conference proceedingConference proceeding

Abstract

In this paper, we introduce a novel reconfigurable hardware architecture for computing the polynomial matrix multiplication (PMM) of polynomial matrices/vectors. The proposed algorithm exploits an extension of the fast convolution technique to multiple-input, multiple-output (MIMO) systems. The proposed architecture is the first one devoted to the hardware implementation of PMM. Hardware implementation of the algorithm is achieved via a highly pipelined, partly systolic FPGA architecture. We verify the algorithmic accuracy of the architecture, which is scalable in terms of the order of the input matrices, through FPGA-in-the-loop hardware co-simulations. Results are presented to demonstrate the accuracy and capability of the architecture.
Original languageEnglish
Title of host publicationProceedings of the 2014 International Conference on Field-Programmable Technology, FPT 2014
PublisherIEEE
Pages243-247
Number of pages5
ISBN (Electronic)978-1-4799-6245-7
DOIs
Publication statusPublished - 9 Apr 2015
Externally publishedYes
Event2014 International Conference on Field-Programmable Technology - Shanghai, Chile
Duration: 10 Dec 201412 Dec 2014

Conference

Conference2014 International Conference on Field-Programmable Technology
Abbreviated titleICFPT
CountryChile
CityShanghai
Period10/12/1412/12/14

Keywords

  • Polynomial Matrix Multiplication
  • SBR2P
  • Xilinx System Generator
  • Field-Programmable Gate Array (FPGA)

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  • Cite this

    Kasap, S., & Redif, S. (2015). Novel reconfigurable hardware implementation of polynomial matrix/vector multiplications. In Proceedings of the 2014 International Conference on Field-Programmable Technology, FPT 2014 (pp. 243-247). IEEE. https://doi.org/10.1109/FPT.2014.7082785