Novel reconfigurable hardware implementation of polynomial matrix/vector multiplications

S. Kasap; S. Redif

doi:10.1109/FPT.2014.7082785

Novel reconfigurable hardware implementation of polynomial matrix/vector multiplications

Research output: Chapter in Book/Report/Conference proceeding › Conference proceeding › peer-review

Abstract

In this paper, we introduce a novel reconfigurable hardware architecture for computing the polynomial matrix multiplication (PMM) of polynomial matrices/vectors. The proposed algorithm exploits an extension of the fast convolution technique to multiple-input, multiple-output (MIMO) systems. The proposed architecture is the first one devoted to the hardware implementation of PMM. Hardware implementation of the algorithm is achieved via a highly pipelined, partly systolic FPGA architecture. We verify the algorithmic accuracy of the architecture, which is scalable in terms of the order of the input matrices, through FPGA-in-the-loop hardware co-simulations. Results are presented to demonstrate the accuracy and capability of the architecture.

Original language	English
Title of host publication	Proceedings of the 2014 International Conference on Field-Programmable Technology, FPT 2014
Publisher	IEEE
Pages	243-247
Number of pages	5
ISBN (Electronic)	978-1-4799-6245-7
DOIs	https://doi.org/10.1109/FPT.2014.7082785
Publication status	Published - 9 Apr 2015
Externally published	Yes
Event	2014 International Conference on Field-Programmable Technology - Shanghai, Chile Duration: 10 Dec 2014 → 12 Dec 2014

Conference

Conference	2014 International Conference on Field-Programmable Technology
Abbreviated title	ICFPT
Country/Territory	Chile
City	Shanghai
Period	10/12/14 → 12/12/14

Keywords

Polynomial Matrix Multiplication
SBR2P
Xilinx System Generator
Field-Programmable Gate Array (FPGA)

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10.1109/FPT.2014.7082785

Cite this

@inproceedings{683c239a514148fe997072fd00737824,

title = "Novel reconfigurable hardware implementation of polynomial matrix/vector multiplications",

abstract = "In this paper, we introduce a novel reconfigurable hardware architecture for computing the polynomial matrix multiplication (PMM) of polynomial matrices/vectors. The proposed algorithm exploits an extension of the fast convolution technique to multiple-input, multiple-output (MIMO) systems. The proposed architecture is the first one devoted to the hardware implementation of PMM. Hardware implementation of the algorithm is achieved via a highly pipelined, partly systolic FPGA architecture. We verify the algorithmic accuracy of the architecture, which is scalable in terms of the order of the input matrices, through FPGA-in-the-loop hardware co-simulations. Results are presented to demonstrate the accuracy and capability of the architecture.",

keywords = "Polynomial Matrix Multiplication, SBR2P, Xilinx System Generator, Field-Programmable Gate Array (FPGA)",

author = "S. Kasap and S. Redif",

year = "2015",

month = apr,

day = "9",

doi = "10.1109/FPT.2014.7082785",

language = "English",

pages = "243--247",

booktitle = "Proceedings of the 2014 International Conference on Field-Programmable Technology, FPT 2014",

publisher = "IEEE",

address = "United States",

note = "2014 International Conference on Field-Programmable Technology , ICFPT ; Conference date: 10-12-2014 Through 12-12-2014",

}

TY - GEN

T1 - Novel reconfigurable hardware implementation of polynomial matrix/vector multiplications

AU - Kasap, S.

AU - Redif, S.

PY - 2015/4/9

Y1 - 2015/4/9

N2 - In this paper, we introduce a novel reconfigurable hardware architecture for computing the polynomial matrix multiplication (PMM) of polynomial matrices/vectors. The proposed algorithm exploits an extension of the fast convolution technique to multiple-input, multiple-output (MIMO) systems. The proposed architecture is the first one devoted to the hardware implementation of PMM. Hardware implementation of the algorithm is achieved via a highly pipelined, partly systolic FPGA architecture. We verify the algorithmic accuracy of the architecture, which is scalable in terms of the order of the input matrices, through FPGA-in-the-loop hardware co-simulations. Results are presented to demonstrate the accuracy and capability of the architecture.

AB - In this paper, we introduce a novel reconfigurable hardware architecture for computing the polynomial matrix multiplication (PMM) of polynomial matrices/vectors. The proposed algorithm exploits an extension of the fast convolution technique to multiple-input, multiple-output (MIMO) systems. The proposed architecture is the first one devoted to the hardware implementation of PMM. Hardware implementation of the algorithm is achieved via a highly pipelined, partly systolic FPGA architecture. We verify the algorithmic accuracy of the architecture, which is scalable in terms of the order of the input matrices, through FPGA-in-the-loop hardware co-simulations. Results are presented to demonstrate the accuracy and capability of the architecture.

KW - Polynomial Matrix Multiplication

KW - SBR2P

KW - Xilinx System Generator

KW - Field-Programmable Gate Array (FPGA)

UR - http://www.scopus.com/inward/record.url?eid=2-s2.0-84928709614&partnerID=MN8TOARS

U2 - 10.1109/FPT.2014.7082785

DO - 10.1109/FPT.2014.7082785

M3 - Conference proceeding

SP - 243

EP - 247

BT - Proceedings of the 2014 International Conference on Field-Programmable Technology, FPT 2014

PB - IEEE

T2 - 2014 International Conference on Field-Programmable Technology

Y2 - 10 December 2014 through 12 December 2014

ER -

Novel reconfigurable hardware implementation of polynomial matrix/vector multiplications

Abstract

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Keywords

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