Novel reconfigurable hardware architecture for polynomial matrix multiplications

S. Redif, S. Kasap

Research output: Contribution to journalArticle

12 Citations (Scopus)

Abstract

In this paper, we introduce a novel reconfigurable hardware architecture for computing the polynomial matrix multiplication (PMM) of polynomial matrices and/or polynomial vectors. The proposed algorithm exploits an extension of the fast convolution technique to multiple-input multiple-output systems. The proposed architecture is the first one devoted to the hardware implementation of PMM. Hardware implementation of the algorithm is achieved via a highly pipelined, partly systolic field-programmable gate array (FPGA) architecture. The architecture, which is scalable in terms of the order of the input polynomial matrices, has been designed using the Xilinx system generator tool. We verify the algorithmic accuracy of the architecture through FPGA-in-the-loop hardware cosimulations. The application to sensor array signal processing is highlighted, in terms of strong decorrelation. The results are presented to demonstrate the accuracy and capability of the architecture. The results verify that the proposed solution gives low execution times while limiting the number of required FPGA resources.
Original languageEnglish
Pages (from-to)454-465
Number of pages12
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume23
Issue number5
Early online date10 Apr 2014
DOIs
Publication statusPublished - Mar 2015
Externally publishedYes

Keywords

  • Field-programmable gate array (FPGA)
  • polynomial matrix computations
  • polynomial matrix multiplication (PMM)
  • SBR2P
  • Xilinx system generator for digital signal processor (DSP) tool.

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