An attractive option for realizing applications in radiation environments is to employ All-Programmable System-on-Chips (APSoCs) thanks to their high-performance computing and power efficiency merits. Despite APSoC’s advantages, like any other electronic device, they are prone to radiation effects. Processors found in APSoCs must, therefore, be adequately hardened against ionizing-radiation to become a viable alternative for harsh environments. This paper proposes a novel triple-core lockstep (TCLS) approach to secure the Xilinx Zynq-7000 APSoC dual-core ARM Cortex-A9 processor against radiation-induced soft errors by coupling it with a MicroBlaze TMR subsystem in Zynq’s programmable logic (PL) layer. The proposed strategy uses software-level checkpointing principles along with roll-back and roll-forward mechanisms (i.e. software redundancy), and hardware-level processor replication as well as checker circuits (i.e. hardware redundancy). Results of fault injection experiments show that the proposed solution achieved high soft error security by mitigating about 99% of bit-flips injected into both ARM cores’ register data.
|Title of host publication||2020 IEEE Nordic Circuits and Systems Conference (NorCAS)|
|Number of pages||7|
|Publication status||E-pub ahead of print - 24 Oct 2020|
|Event||2020 IEEE Nordic Circuits and Systems Conference - virtual, Oslo, Norway|
Duration: 27 Nov 2020 → 28 Nov 2020
|Conference||2020 IEEE Nordic Circuits and Systems Conference|
|Period||27/11/20 → 28/11/20|
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- Fault Tolerance
- Soft Error Mitigation
- Zynq APSoC
- ARM Cortex-A Processor
- MicroBlaze Processor