Novel 2-D RESURF LDMOSFET in 0.6 /spl mu/m CMOS technology for power ICs

P.M. Holland, T.K.H. Starke, S. Hussain, W.M. Jamal, P.A. Mawby, P.M. Igic

Research output: Chapter in Book/Report/Conference proceedingConference proceeding

Abstract

A 0.6 /spl mu/m CMOS process was adapted to incorporate LDMOS transistors for Power Integrated Circuit Applications. The design was realised by adding only three additional ion implants process steps and one extra masking process step providing a cost effective approach. The design was optimised prior to manufacture by the Avanti TCAD simulation tool. Physical results show good agreement with the simulated device and display 2-D RESURF action.
Original languageEnglish
Title of host publication2004 24th International Conference on Microelectronics (IEEE Cat. No.04TH8716)
PublisherIEEE
Pages133-136
Number of pages4
Volume1
ISBN (Print)0-7803-8166-1
DOIs
Publication statusPublished - 19 May 2004
Externally publishedYes
Event2004 24th International Conference on Microelectronics - Nis, Serbia, Nis, Serbia
Duration: 16 May 200419 May 2004
Conference number: 24

Conference

Conference2004 24th International Conference on Microelectronics
Abbreviated titleMIEL 2004
Country/TerritorySerbia
CityNis
Period16/05/0419/05/04

Keywords

  • CMOS technology
  • Power integrated circuits
  • Circuit simulation
  • Integrated circuit technology
  • CMOS process
  • Implants
  • Costs
  • Design optimization
  • Virtual manufacturing
  • Displays

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