Novel 2-D RESURF LDMOSFET in 0.6μm CMOS technology for power ICs

P. M. Holland, T. K.H. Starke, S. Hussain, W. M. Jamal, P. A. Mawby, P. M. Igic

Research output: Contribution to conferencePaper

Abstract

A 0.6um CMOS process was adapted to incorporate LDMOS transistors for Power Integrated Circuit Applications. The design was realised by adding only three additional ion implants process steps and one extra masking process step providing a cost effective approach. The design was optimised prior to manufacture by the Avanti TCAD simulation tool. Physical results show good agreement with the simulated device and display 2-D RESURF action.

Original languageEnglish
Number of pages4
Publication statusPublished - 28 Jul 2004
Externally publishedYes
Event24th International Conference on Microelectronics - Nis, Serbia
Duration: 16 May 200419 May 2004
Conference number: 24

Conference

Conference24th International Conference on Microelectronics
Abbreviated titleMIEL 2004
CountrySerbia
CityNis
Period16/05/0419/05/04

ASJC Scopus subject areas

  • Engineering(all)

Fingerprint Dive into the research topics of 'Novel 2-D RESURF LDMOSFET in 0.6μm CMOS technology for power ICs'. Together they form a unique fingerprint.

  • Cite this

    Holland, P. M., Starke, T. K. H., Hussain, S., Jamal, W. M., Mawby, P. A., & Igic, P. M. (2004). Novel 2-D RESURF LDMOSFET in 0.6μm CMOS technology for power ICs. Paper presented at 24th International Conference on Microelectronics, Nis, Serbia.