Abstract
This study presents a new topology of single-phase cascaded multilevel inverter (CMLI). The proposed topology offers an optimised DC source utilisation, reduced switch count and curtailment of active switches in the conduction path for minimising power losses. It can produce almost twice the number of output voltage steps in comparison to the cascaded H-bridge, hence named level-doubling architecture, and can be operated as both symmetric and asymmetric CMLIs. Identical modules of proposed CMLI precludes requirement of a variety of semiconductors and provides ease for spare management. The modular design also facilitates mass production and enhances system reliability. Furthermore, the proposed topology can be easily extended to high-voltage applications. The proposed design is tested for its practicability by simulations in MATLAB/ Simulink and results are verified by experimental set up of a scaled prototype single-phase model.
| Original language | English |
|---|---|
| Pages (from-to) | 1891-1902 |
| Number of pages | 12 |
| Journal | IET Power Electronics |
| Volume | 12 |
| Issue number | 8 |
| Early online date | 26 Mar 2019 |
| DOIs | |
| Publication status | Published - 10 Jul 2019 |
Bibliographical note
"This paper is a postprint of a paper submitted to and accepted for publication in IET Power Electronics and is subject to Institution of Engineering and TechnologyCopyright. The copy of record is available at the IET Digital Library”
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ASJC Scopus subject areas
- Electrical and Electronic Engineering