New level doubling architecture of cascaded Multilevel inverter

Arfan Ghani, Ashraf Yahya, Syed M Usman Ali

Research output: Contribution to journalArticle

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Abstract

This study presents a new topology of single-phase cascaded multilevel inverter (CMLI). The proposed topology offers an optimised DC source utilisation, reduced switch count and curtailment of active switches in the conduction path for minimising power losses. It can produce almost twice the number of output voltage steps in comparison to the cascaded H-bridge, hence named level-doubling architecture, and can be operated as both symmetric and asymmetric CMLIs. Identical modules of proposed CMLI precludes requirement of a variety of semiconductors and provides ease for spare management. The modular design also facilitates mass production and enhances system reliability. Furthermore, the proposed topology can be easily extended to high-voltage applications. The proposed design is tested for its practicability by simulations in MATLAB/ Simulink and results are verified by experimental set up of a scaled prototype single-phase model.

Original languageEnglish
Pages (from-to)1891-1902
Number of pages12
JournalIET Power Electronics
Volume12
Issue number8
Early online date26 Mar 2019
DOIs
Publication statusPublished - 10 Jul 2019

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Topology
Switches
Electric potential
MATLAB
Semiconductor materials

Bibliographical note

"This paper is a postprint of a paper submitted to and accepted for publication in IET Power Electronics and is subject to Institution of Engineering and Technology
Copyright. The copy of record is available at the IET Digital Library”

Copyright © and Moral Rights are retained by the author(s) and/ or other copyright owners. A copy can be downloaded for personal non-commercial research or study, without prior permission or charge. This item cannot be reproduced or quoted extensively from without first obtaining permission in writing from the copyright holder(s). The content must not be changed in any way or sold commercially in any format or medium without the formal permission of the copyright holders

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

New level doubling architecture of cascaded Multilevel inverter. / Ghani, Arfan; Yahya, Ashraf; Ali, Syed M Usman.

In: IET Power Electronics, Vol. 12, No. 8, 10.07.2019, p. 1891-1902.

Research output: Contribution to journalArticle

Ghani, Arfan ; Yahya, Ashraf ; Ali, Syed M Usman. / New level doubling architecture of cascaded Multilevel inverter. In: IET Power Electronics. 2019 ; Vol. 12, No. 8. pp. 1891-1902.
@article{c0a660a8b28848b89ad686ef5adfcf4a,
title = "New level doubling architecture of cascaded Multilevel inverter",
abstract = "This study presents a new topology of single-phase cascaded multilevel inverter (CMLI). The proposed topology offers an optimised DC source utilisation, reduced switch count and curtailment of active switches in the conduction path for minimising power losses. It can produce almost twice the number of output voltage steps in comparison to the cascaded H-bridge, hence named level-doubling architecture, and can be operated as both symmetric and asymmetric CMLIs. Identical modules of proposed CMLI precludes requirement of a variety of semiconductors and provides ease for spare management. The modular design also facilitates mass production and enhances system reliability. Furthermore, the proposed topology can be easily extended to high-voltage applications. The proposed design is tested for its practicability by simulations in MATLAB/ Simulink and results are verified by experimental set up of a scaled prototype single-phase model.",
author = "Arfan Ghani and Ashraf Yahya and Ali, {Syed M Usman}",
note = "{"}This paper is a postprint of a paper submitted to and accepted for publication in IET Power Electronics and is subject to Institution of Engineering and Technology Copyright. The copy of record is available at the IET Digital Library” Copyright {\circledC} and Moral Rights are retained by the author(s) and/ or other copyright owners. A copy can be downloaded for personal non-commercial research or study, without prior permission or charge. This item cannot be reproduced or quoted extensively from without first obtaining permission in writing from the copyright holder(s). The content must not be changed in any way or sold commercially in any format or medium without the formal permission of the copyright holders",
year = "2019",
month = "7",
day = "10",
doi = "10.1049/iet-pel.2018.5512",
language = "English",
volume = "12",
pages = "1891--1902",
journal = "IET Power Electronics",
issn = "1755-4535",
publisher = "Institution of Engineering and Technology",
number = "8",

}

TY - JOUR

T1 - New level doubling architecture of cascaded Multilevel inverter

AU - Ghani, Arfan

AU - Yahya, Ashraf

AU - Ali, Syed M Usman

N1 - "This paper is a postprint of a paper submitted to and accepted for publication in IET Power Electronics and is subject to Institution of Engineering and Technology Copyright. The copy of record is available at the IET Digital Library” Copyright © and Moral Rights are retained by the author(s) and/ or other copyright owners. A copy can be downloaded for personal non-commercial research or study, without prior permission or charge. This item cannot be reproduced or quoted extensively from without first obtaining permission in writing from the copyright holder(s). The content must not be changed in any way or sold commercially in any format or medium without the formal permission of the copyright holders

PY - 2019/7/10

Y1 - 2019/7/10

N2 - This study presents a new topology of single-phase cascaded multilevel inverter (CMLI). The proposed topology offers an optimised DC source utilisation, reduced switch count and curtailment of active switches in the conduction path for minimising power losses. It can produce almost twice the number of output voltage steps in comparison to the cascaded H-bridge, hence named level-doubling architecture, and can be operated as both symmetric and asymmetric CMLIs. Identical modules of proposed CMLI precludes requirement of a variety of semiconductors and provides ease for spare management. The modular design also facilitates mass production and enhances system reliability. Furthermore, the proposed topology can be easily extended to high-voltage applications. The proposed design is tested for its practicability by simulations in MATLAB/ Simulink and results are verified by experimental set up of a scaled prototype single-phase model.

AB - This study presents a new topology of single-phase cascaded multilevel inverter (CMLI). The proposed topology offers an optimised DC source utilisation, reduced switch count and curtailment of active switches in the conduction path for minimising power losses. It can produce almost twice the number of output voltage steps in comparison to the cascaded H-bridge, hence named level-doubling architecture, and can be operated as both symmetric and asymmetric CMLIs. Identical modules of proposed CMLI precludes requirement of a variety of semiconductors and provides ease for spare management. The modular design also facilitates mass production and enhances system reliability. Furthermore, the proposed topology can be easily extended to high-voltage applications. The proposed design is tested for its practicability by simulations in MATLAB/ Simulink and results are verified by experimental set up of a scaled prototype single-phase model.

UR - http://www.scopus.com/inward/record.url?scp=85069057570&partnerID=8YFLogxK

U2 - 10.1049/iet-pel.2018.5512

DO - 10.1049/iet-pel.2018.5512

M3 - Article

VL - 12

SP - 1891

EP - 1902

JO - IET Power Electronics

JF - IET Power Electronics

SN - 1755-4535

IS - 8

ER -