New LDMOS transistor based on 0.6u CMOS technology for power IC applications

S. Hussain, P. M. Holland, T. Starke, P. M. Igic, P. A. Mawby

Research output: Chapter in Book/Report/Conference proceedingConference proceeding

Abstract

New LDMOSFET device based on 0.6 microns CMOS technology (X-Fab Plymouth, UK) is presented in this paper. The process is based on p-(substrate)/p-(epi) layers, layer thicknesses and dopings being standard for this type of technology. The optimised device has a 75 V breakdown voltage.

Original languageEnglish
Title of host publicationICSE 2002 - 2002 IEEE International Conference on Semiconductor Electronics, Proceedings
Pages169-171
Number of pages3
Publication statusPublished - 1 Dec 2002
Externally publishedYes
Event2002 5th IEEE International Conference on Semiconductor Electronics, ICSE 2002 - Penang, Malaysia
Duration: 19 Dec 200221 Dec 2002

Publication series

NameIEEE International Conference on Semiconductor Electronics, Proceedings, ICSE

Conference

Conference2002 5th IEEE International Conference on Semiconductor Electronics, ICSE 2002
CountryMalaysia
CityPenang
Period19/12/0221/12/02

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Fingerprint Dive into the research topics of 'New LDMOS transistor based on 0.6u CMOS technology for power IC applications'. Together they form a unique fingerprint.

  • Cite this

    Hussain, S., Holland, P. M., Starke, T., Igic, P. M., & Mawby, P. A. (2002). New LDMOS transistor based on 0.6u CMOS technology for power IC applications. In ICSE 2002 - 2002 IEEE International Conference on Semiconductor Electronics, Proceedings (pp. 169-171). [1217798] (IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE).