Mechanical stress related instabilities in silicon under metal coverage

Dragan Manic, Peter M. Igic, Phil A. Mawby, Youcef Haddab, Radivoje S. Popovic

Research output: Contribution to journalArticlepeer-review

12 Citations (Scopus)


Mechanical stress related instabilities in silicon bulk material under integrated circuits (ICs) metallization are investigated. The test structures based on Wheatstone bridge configuration in which two out of four resistors were covered by wide aluminum stripes were fabricated especially for this purpose. Calculations based on the piezoresistance effect were utilized to estimate the mechanical stress in the silicon substrate. Also, finite element modeling (FEM) of the fabricated test structures has been performed. Both results, experimental and numerical, show that metallization involves an additional stress term in the silicon buffer. The piezoresistance can influence the matching characteristics of ICs and also produce a time-drift of IC performance due to the time-drift of mechanical stress. Resistance mismatching of more than 1000 ppm was measured when the resistors were covered by aluminum. A covered resistance drift of 245 ppm due to aluminum plastic deformation was measured when heating tests were applied. Finally, the simulation results for the prediction of the stress levels in silicon covered with metal lines of various widths are presented. For a 4 μm-width aluminum line it was recognized a safe distance of 10 μm.

Original languageEnglish
Pages (from-to)2429-2437
Number of pages9
JournalIEEE Transactions on Electron Devices
Issue number12
Publication statusPublished - 1 Dec 2000
Externally publishedYes


  • Aluminum
  • FEM
  • Long-term drift
  • Matching
  • Piezoresistance
  • Silicon
  • Stress

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering


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