Highly effective junction isolation structures for PICs based on standard CMOS process

Thomas K.H. Starke; Paul M. Holland; Shahzad Hussain; W. M. Jamal; P. A. Mawby; Petar M. Igic

doi:10.1109/TED.2004.829895

Highly effective junction isolation structures for PICs based on standard CMOS process

Thomas K.H. Starke, Paul M. Holland, Shahzad Hussain, W. M. Jamal, P. A. Mawby, Petar M. Igic

Swansea University

Research output: Contribution to journal › Article › peer-review

14 Citations (Scopus)

Abstract

This paper presents novel and highly effective junction isolation structures for power integrated circuits. The negative feedback-activated junction isolation is presented and it is proven to be very effective in blocking substrate current from reaching the logic circuitry (orders of magnitude more effective than standard junction isolation techniques). Additionally, in an attempt to further improve the blocking capabilities of junction isolations the use of multiple or combined structures is investigated whilst keeping the surface area used for isolation device in the same range as for the single structures. All isolation structures presented here are based on a 0.6-μm CMOS technology.

Original language	English
Article number	1308644
Pages (from-to)	1178-1184
Number of pages	7
Journal	IEEE Transactions on Electron Devices
Volume	51
Issue number	7
DOIs	https://doi.org/10.1109/TED.2004.829895
Publication status	Published - 28 Jun 2004
Externally published	Yes

Keywords

Power integrated circuits
CMOSFET logic devices
Logic design
Isolation technology

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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10.1109/TED.2004.829895

https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1308644

Cite this

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title = "Highly effective junction isolation structures for PICs based on standard CMOS process",

abstract = "This paper presents novel and highly effective junction isolation structures for power integrated circuits. The negative feedback-activated junction isolation is presented and it is proven to be very effective in blocking substrate current from reaching the logic circuitry (orders of magnitude more effective than standard junction isolation techniques). Additionally, in an attempt to further improve the blocking capabilities of junction isolations the use of multiple or combined structures is investigated whilst keeping the surface area used for isolation device in the same range as for the single structures. All isolation structures presented here are based on a 0.6-μm CMOS technology.",

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AU - Starke, Thomas K.H.

AU - Holland, Paul M.

AU - Hussain, Shahzad

AU - Jamal, W. M.

AU - Mawby, P. A.

AU - Igic, Petar M.

PY - 2004/6/28

Y1 - 2004/6/28

N2 - This paper presents novel and highly effective junction isolation structures for power integrated circuits. The negative feedback-activated junction isolation is presented and it is proven to be very effective in blocking substrate current from reaching the logic circuitry (orders of magnitude more effective than standard junction isolation techniques). Additionally, in an attempt to further improve the blocking capabilities of junction isolations the use of multiple or combined structures is investigated whilst keeping the surface area used for isolation device in the same range as for the single structures. All isolation structures presented here are based on a 0.6-μm CMOS technology.

AB - This paper presents novel and highly effective junction isolation structures for power integrated circuits. The negative feedback-activated junction isolation is presented and it is proven to be very effective in blocking substrate current from reaching the logic circuitry (orders of magnitude more effective than standard junction isolation techniques). Additionally, in an attempt to further improve the blocking capabilities of junction isolations the use of multiple or combined structures is investigated whilst keeping the surface area used for isolation device in the same range as for the single structures. All isolation structures presented here are based on a 0.6-μm CMOS technology.

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KW - CMOSFET logic devices

KW - Logic design

KW - Isolation technology

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ER -

Highly effective junction isolation structures for PICs based on standard CMOS process

Abstract

Keywords

ASJC Scopus subject areas

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