Highly effective junction isolation structures for PICs based on standard CMOS process

Thomas K.H. Starke, Paul M. Holland, Shahzad Hussain, W. M. Jamal, P. A. Mawby, Petar M. Igic

Research output: Contribution to journalArticlepeer-review

14 Citations (Scopus)


This paper presents novel and highly effective junction isolation structures for power integrated circuits. The negative feedback-activated junction isolation is presented and it is proven to be very effective in blocking substrate current from reaching the logic circuitry (orders of magnitude more effective than standard junction isolation techniques). Additionally, in an attempt to further improve the blocking capabilities of junction isolations the use of multiple or combined structures is investigated whilst keeping the surface area used for isolation device in the same range as for the single structures. All isolation structures presented here are based on a 0.6-μm CMOS technology.

Original languageEnglish
Article number1308644
Pages (from-to)1178-1184
Number of pages7
JournalIEEE Transactions on Electron Devices
Issue number7
Publication statusPublished - 28 Jun 2004
Externally publishedYes


  • Power integrated circuits
  • CMOSFET logic devices
  • Logic design
  • Isolation technology

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering


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