Polynomial matrix computations, such as polynomial matrix multiplication (PMM) and eigenvalue factorization of parahermitian matrices, have played an important role in a growing number of applications, in recent times. However, the computational complexity and expense of such operations impose a profound limit on their applicability. In a recent paper, we introduced a systolic array-based parallel architecture for PMM, which was adequately efficient, but limited in its application. In this paper, we propose a second-generation hardware solution which boasts more versatility, efficiency and scalability compared to our previous design. This is achieved through the design of a highly versatile PMM accelerator which supports polynomial matrices of any size, as a component of the embedded system developed within the Xilinx Zynq-7000 AP SoC. Experimental results demonstrate the efficiency and effectiveness of our novel SoC-based PMM accelerator in the context of subband coding, where maximum speedups of 85× and 33× are accomplished, without compromising the accuracy, in comparison with two highly optimized and multi-threaded software-only implementations running on a dual-core ARM Cortex-A9 processor and a Intel Core i7-4510U CPU, respectively.
- Polynomial matrix multiplication
- Polynomial matrix computations
- Computer architecture
- Hardware/software co-design
- System-on-chip (SoC)
- Zynq-7000 AP SoC