>10kV 4H-SiC n-IGBTs for Elevated Temperature Environments

Samuel Perkins; Marina Antoniou; Amit K. Tiwari; Anastasios Arvanitopoulos; T. Trajkovic; Florin Udrea; Neophytos Lophitis

>10kV 4H-SiC n-IGBTs for Elevated Temperature Environments

Samuel Perkins, Marina Antoniou, Amit K. Tiwari, Anastasios Arvanitopoulos, T. Trajkovic, Florin Udrea, Neophytos Lophitis

University of Cambridge

Research output: Contribution to conference › Paper › peer-review

Abstract

In this work we explore the appropriate design parameters which will enable the fabrication of a >10kVn-Channel IGBT. In particular, we emphasize the reduction of device blocking capabilities for high temperature environments. Moreover, this work shows that the SiC device design optimization methodology needs to be rethought to account for the significant loss of blocking voltage at the desired elevated operating temperatures. Indeed, device design engineers aiming to optimize a SiC IGBT should design at high temperature and not at room temperature.

Original language	English
Publication status	Published - Aug 2018
Event	The 14th International Seminar on Power Semiconductors (ISPS 2018) - Prague, Czech Republic Duration: 29 Aug 2018 → 31 Aug 2018 http://technology.feld.cvut.cz:8080/xwiki/bin/view/ISPS2018/

Conference

Conference	The 14th International Seminar on Power Semiconductors (ISPS 2018)
Abbreviated title	ISPS
Country/Territory	Czech Republic
City	Prague
Period	29/08/18 → 31/08/18
Internet address	http://technology.feld.cvut.cz:8080/xwiki/bin/view/ISPS2018/

Keywords

4H-SiC
Blocking Voltage,
Temperature
IGBT
High-Voltage
Optimization.

Cite this

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title = ">10kV 4H-SiC n-IGBTs for Elevated Temperature Environments",

abstract = "In this work we explore the appropriate design parameters which will enable the fabrication of a >10kVn-Channel IGBT. In particular, we emphasize the reduction of device blocking capabilities for high temperature environments. Moreover, this work shows that the SiC device design optimization methodology needs to be rethought to account for the significant loss of blocking voltage at the desired elevated operating temperatures. Indeed, device design engineers aiming to optimize a SiC IGBT should design at high temperature and not at room temperature.",

keywords = "4H-SiC, Blocking Voltage,, Temperature, IGBT, High-Voltage, Optimization.",

author = "Samuel Perkins and Marina Antoniou and {K. Tiwari}, Amit and Anastasios Arvanitopoulos and T. Trajkovic and Florin Udrea and Neophytos Lophitis",

year = "2018",

month = aug,

language = "English",

note = "The 14th International Seminar on Power Semiconductors (ISPS 2018), ISPS ; Conference date: 29-08-2018 Through 31-08-2018",

url = "http://technology.feld.cvut.cz:8080/xwiki/bin/view/ISPS2018/",

}

TY - CONF

T1 - >10kV 4H-SiC n-IGBTs for Elevated Temperature Environments

AU - Perkins, Samuel

AU - Antoniou, Marina

AU - K. Tiwari, Amit

AU - Arvanitopoulos, Anastasios

AU - Trajkovic, T.

AU - Udrea, Florin

AU - Lophitis, Neophytos

PY - 2018/8

Y1 - 2018/8

N2 - In this work we explore the appropriate design parameters which will enable the fabrication of a >10kVn-Channel IGBT. In particular, we emphasize the reduction of device blocking capabilities for high temperature environments. Moreover, this work shows that the SiC device design optimization methodology needs to be rethought to account for the significant loss of blocking voltage at the desired elevated operating temperatures. Indeed, device design engineers aiming to optimize a SiC IGBT should design at high temperature and not at room temperature.

AB - In this work we explore the appropriate design parameters which will enable the fabrication of a >10kVn-Channel IGBT. In particular, we emphasize the reduction of device blocking capabilities for high temperature environments. Moreover, this work shows that the SiC device design optimization methodology needs to be rethought to account for the significant loss of blocking voltage at the desired elevated operating temperatures. Indeed, device design engineers aiming to optimize a SiC IGBT should design at high temperature and not at room temperature.

KW - 4H-SiC

KW - Blocking Voltage,

KW - Temperature

KW - IGBT

KW - High-Voltage

KW - Optimization.

UR - http://technology.feld.cvut.cz/ISPS2018

M3 - Paper

T2 - The 14th International Seminar on Power Semiconductors (ISPS 2018)

Y2 - 29 August 2018 through 31 August 2018

ER -

>10kV 4H-SiC n-IGBTs for Elevated Temperature Environments

Abstract

Conference

Keywords

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