FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm

S. Kasap, Soydan Redif

Research output: Chapter in Book/Report/Conference proceedingConference proceeding

1 Citation (Scopus)

Abstract

In this paper, we introduce a field-programmable gate array (FPGA) hardware architecture for the realization of an algorithm for computing the eigenvalue decomposition (EVD) of para-Hermitian polynomial matrices. Specifically, we develop a parallelized version of the second-order sequential best rotation (SBR2) algorithm for polynomial matrix EVD (PEVD). The proposed algorithm is an extension of the parallel Jacobi method to para-Hermitian polynomial matrices, as such it is the first architecture devoted to PEVD. Hardware implementation of the algorithm is achieved via a highly pipelined, non-systolic FPGA architecture. The proposed architecture is scalable in terms of the size of the input para-Hermitian matrix. We demonstrate the decomposition accuracy of the architecture through FPGA-in-the-loop hardware co-simulations. Results confirm that the proposed solution gives low execution times while reducing the number of resources required from the FPGA.
Original languageEnglish
Title of host publication2012 International Conference on Field-Programmable Technology
PublisherIEEE
Pages135 - 140
Number of pages6
ISBN (Electronic)978-1-4673-2844-9
ISBN (Print)978-1-4673-2846-3
DOIs
Publication statusPublished - 2012
Externally publishedYes
EventInternational Conference on Field-Programmable Technology - Seoul, Korea, Republic of
Duration: 10 Dec 201212 Dec 2012

Conference

ConferenceInternational Conference on Field-Programmable Technology
Abbreviated titleFPT 2012
CountryKorea, Republic of
City Seoul
Period10/12/1212/12/12

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  • Cite this

    Kasap, S., & Redif, S. (2012). FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm. In 2012 International Conference on Field-Programmable Technology (pp. 135 - 140). IEEE. https://doi.org/10.1109/FPT.2012.6412125