Fault collapsing and test generation for a circuit

Moslem Amiri, Václav Přenosil

    Research output: Chapter in Book/Report/Conference proceedingConference proceedingpeer-review


    A novel method to generate a complete list of faults and their corresponding test vectors for a gate-level circuit is presented. This method creates the distinguishable faults of a circuit based on the paths they propagate, along with the test vector(s) for each fault. While the other available methods for fault list and test vector generation are expensive, this method tries to reduce the cost by avoiding all the unnecessary steps and merging the two tasks together.
    Original languageEnglish
    Title of host publication Deterioration, Dependability, Diagnostics 2013
    Place of PublicationBrno, Czech Republic
    PublisherUniversity of Defence
    Number of pages7
    ISBN (Print)978-80-7231-939-8
    Publication statusPublished - Oct 2013


    • Fault list generation
    • test vector generation
    • fault paths


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