Abstract
A novel method to generate a complete list of faults and their corresponding test vectors for a gate-level circuit is presented. This method creates the distinguishable faults of a circuit based on the paths they propagate, along with the test vector(s) for each fault. While the other available methods for fault list and test vector generation are expensive, this method tries to reduce the cost by avoiding all the unnecessary steps and merging the two tasks together.
| Original language | English |
|---|---|
| Title of host publication | Deterioration, Dependability, Diagnostics 2013 |
| Place of Publication | Brno, Czech Republic |
| Publisher | University of Defence |
| Pages | 55–61 |
| Number of pages | 7 |
| ISBN (Print) | 978-80-7231-939-8 |
| Publication status | Published - Oct 2013 |
Keywords
- Fault list generation
- test vector generation
- fault paths