In this paper we present a wafer level three-dimensional simulation model of the Gate Commutated Thyristor (GCT) under inductive switching conditions. The simulations are validated by extensive experimental measurements. To the authors' knowledge such a complex simulation domain has not been used so far. This method allows the in depth study of large area devices such as GCTs, Gate Turn Off Thyristors (GTOs) and Phase Control Thyristors (PCTs). The model captures complex phenomena, such as current filamentation including subsequent failure, which allow us to predict the Maximum Controllable turn-off Current (MCC) and the Safe Operating Area (SOA) previously impossible using 2D distributed models.
|Title of host publication||Proceedings of the 2012 24th International Symposium on Power Semiconductor Devices and ICs, ISPSD'12|
|Number of pages||4|
|Publication status||Published - 2012|
|Event||24th International Symposium on Power Semiconductor Devices and ICs, ISPSD'12 - Bruges, Belgium|
Duration: 3 Jun 2012 → 7 Jun 2012
|Conference||24th International Symposium on Power Semiconductor Devices and ICs, ISPSD'12|
|Period||3/06/12 → 7/06/12|
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