Abstract
In this paper we present a wafer level three-dimensional simulation model of the Gate Commutated Thyristor (GCT) under inductive switching conditions. The simulations are validated by extensive experimental measurements. To the authors' knowledge such a complex simulation domain has not been used so far. This method allows the in depth study of large area devices such as GCTs, Gate Turn Off Thyristors (GTOs) and Phase Control Thyristors (PCTs). The model captures complex phenomena, such as current filamentation including subsequent failure, which allow us to predict the Maximum Controllable turn-off Current (MCC) and the Safe Operating Area (SOA) previously impossible using 2D distributed models.
| Original language | English |
|---|---|
| Title of host publication | Proceedings of the 2012 24th International Symposium on Power Semiconductor Devices and ICs, ISPSD'12 |
| Publisher | IEEE |
| Pages | 349-352 |
| Number of pages | 4 |
| ISBN (Print) | 9781457715952 |
| DOIs | |
| Publication status | Published - 2012 |
| Externally published | Yes |
| Event | 24th International Symposium on Power Semiconductor Devices and ICs, ISPSD'12 - Bruges, Belgium Duration: 3 Jun 2012 → 7 Jun 2012 |
Conference
| Conference | 24th International Symposium on Power Semiconductor Devices and ICs, ISPSD'12 |
|---|---|
| Country | Belgium |
| City | Bruges |
| Period | 3/06/12 → 7/06/12 |
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Bibliographical note
© 2012 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.ASJC Scopus subject areas
- Engineering(all)
Cite this
Experimentally validated three dimensional GCT wafer level simulations. / Lophitis, N.; Antoniou, M.; Udrea, F.; Nistor, I.; Arnold, M.; Wikström, T.; Vobecky, J.
Proceedings of the 2012 24th International Symposium on Power Semiconductor Devices and ICs, ISPSD'12. IEEE, 2012. p. 349-352 6229093.Research output: Chapter in Book/Report/Conference proceeding › Conference proceeding
}
TY - GEN
T1 - Experimentally validated three dimensional GCT wafer level simulations
AU - Lophitis, N.
AU - Antoniou, M.
AU - Udrea, F.
AU - Nistor, I.
AU - Arnold, M.
AU - Wikström, T.
AU - Vobecky, J.
N1 - © 2012 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
PY - 2012
Y1 - 2012
N2 - In this paper we present a wafer level three-dimensional simulation model of the Gate Commutated Thyristor (GCT) under inductive switching conditions. The simulations are validated by extensive experimental measurements. To the authors' knowledge such a complex simulation domain has not been used so far. This method allows the in depth study of large area devices such as GCTs, Gate Turn Off Thyristors (GTOs) and Phase Control Thyristors (PCTs). The model captures complex phenomena, such as current filamentation including subsequent failure, which allow us to predict the Maximum Controllable turn-off Current (MCC) and the Safe Operating Area (SOA) previously impossible using 2D distributed models.
AB - In this paper we present a wafer level three-dimensional simulation model of the Gate Commutated Thyristor (GCT) under inductive switching conditions. The simulations are validated by extensive experimental measurements. To the authors' knowledge such a complex simulation domain has not been used so far. This method allows the in depth study of large area devices such as GCTs, Gate Turn Off Thyristors (GTOs) and Phase Control Thyristors (PCTs). The model captures complex phenomena, such as current filamentation including subsequent failure, which allow us to predict the Maximum Controllable turn-off Current (MCC) and the Safe Operating Area (SOA) previously impossible using 2D distributed models.
U2 - 10.1109/ISPSD.2012.6229093
DO - 10.1109/ISPSD.2012.6229093
M3 - Conference proceeding
SN - 9781457715952
SP - 349
EP - 352
BT - Proceedings of the 2012 24th International Symposium on Power Semiconductor Devices and ICs, ISPSD'12
PB - IEEE
ER -