Experimentally validated three dimensional GCT wafer level simulations

N. Lophitis, M. Antoniou, F. Udrea, I. Nistor, M. Arnold, T. Wikström, J. Vobecky

Research output: Chapter in Book/Report/Conference proceedingConference proceeding

7 Citations (Scopus)
13 Downloads (Pure)

Abstract

In this paper we present a wafer level three-dimensional simulation model of the Gate Commutated Thyristor (GCT) under inductive switching conditions. The simulations are validated by extensive experimental measurements. To the authors' knowledge such a complex simulation domain has not been used so far. This method allows the in depth study of large area devices such as GCTs, Gate Turn Off Thyristors (GTOs) and Phase Control Thyristors (PCTs). The model captures complex phenomena, such as current filamentation including subsequent failure, which allow us to predict the Maximum Controllable turn-off Current (MCC) and the Safe Operating Area (SOA) previously impossible using 2D distributed models.

Original languageEnglish
Title of host publicationProceedings of the 2012 24th International Symposium on Power Semiconductor Devices and ICs, ISPSD'12
PublisherIEEE
Pages349-352
Number of pages4
ISBN (Print)9781457715952
DOIs
Publication statusPublished - 2012
Externally publishedYes
Event24th International Symposium on Power Semiconductor Devices and ICs, ISPSD'12 - Bruges, Belgium
Duration: 3 Jun 20127 Jun 2012

Conference

Conference24th International Symposium on Power Semiconductor Devices and ICs, ISPSD'12
CountryBelgium
CityBruges
Period3/06/127/06/12

Fingerprint

Thyristors
Phase control

Bibliographical note

© 2012 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Lophitis, N., Antoniou, M., Udrea, F., Nistor, I., Arnold, M., Wikström, T., & Vobecky, J. (2012). Experimentally validated three dimensional GCT wafer level simulations. In Proceedings of the 2012 24th International Symposium on Power Semiconductor Devices and ICs, ISPSD'12 (pp. 349-352). [6229093] IEEE. https://doi.org/10.1109/ISPSD.2012.6229093

Experimentally validated three dimensional GCT wafer level simulations. / Lophitis, N.; Antoniou, M.; Udrea, F.; Nistor, I.; Arnold, M.; Wikström, T.; Vobecky, J.

Proceedings of the 2012 24th International Symposium on Power Semiconductor Devices and ICs, ISPSD'12. IEEE, 2012. p. 349-352 6229093.

Research output: Chapter in Book/Report/Conference proceedingConference proceeding

Lophitis, N, Antoniou, M, Udrea, F, Nistor, I, Arnold, M, Wikström, T & Vobecky, J 2012, Experimentally validated three dimensional GCT wafer level simulations. in Proceedings of the 2012 24th International Symposium on Power Semiconductor Devices and ICs, ISPSD'12., 6229093, IEEE, pp. 349-352, 24th International Symposium on Power Semiconductor Devices and ICs, ISPSD'12, Bruges, Belgium, 3/06/12. https://doi.org/10.1109/ISPSD.2012.6229093
Lophitis N, Antoniou M, Udrea F, Nistor I, Arnold M, Wikström T et al. Experimentally validated three dimensional GCT wafer level simulations. In Proceedings of the 2012 24th International Symposium on Power Semiconductor Devices and ICs, ISPSD'12. IEEE. 2012. p. 349-352. 6229093 https://doi.org/10.1109/ISPSD.2012.6229093
Lophitis, N. ; Antoniou, M. ; Udrea, F. ; Nistor, I. ; Arnold, M. ; Wikström, T. ; Vobecky, J. / Experimentally validated three dimensional GCT wafer level simulations. Proceedings of the 2012 24th International Symposium on Power Semiconductor Devices and ICs, ISPSD'12. IEEE, 2012. pp. 349-352
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