Experimentally validated three dimensional GCT wafer level simulations

N. Lophitis; M. Antoniou; F. Udrea; I. Nistor; M. Arnold; T. Wikström; J. Vobecky

doi:10.1109/ISPSD.2012.6229093

Experimentally validated three dimensional GCT wafer level simulations

N. Lophitis, M. Antoniou, F. Udrea, I. Nistor, M. Arnold, T. Wikström, J. Vobecky

Research output: Chapter in Book/Report/Conference proceeding › Conference proceeding › peer-review

10 Citations (Scopus)

35 Downloads (Pure)

Abstract

In this paper we present a wafer level three-dimensional simulation model of the Gate Commutated Thyristor (GCT) under inductive switching conditions. The simulations are validated by extensive experimental measurements. To the authors' knowledge such a complex simulation domain has not been used so far. This method allows the in depth study of large area devices such as GCTs, Gate Turn Off Thyristors (GTOs) and Phase Control Thyristors (PCTs). The model captures complex phenomena, such as current filamentation including subsequent failure, which allow us to predict the Maximum Controllable turn-off Current (MCC) and the Safe Operating Area (SOA) previously impossible using 2D distributed models.

Original language	English
Title of host publication	Proceedings of the 2012 24th International Symposium on Power Semiconductor Devices and ICs, ISPSD'12
Publisher	IEEE
Pages	349-352
Number of pages	4
ISBN (Print)	9781457715952
DOIs	https://doi.org/10.1109/ISPSD.2012.6229093
Publication status	Published - 2012
Externally published	Yes
Event	24th International Symposium on Power Semiconductor Devices and ICs - Bruges, Belgium Duration: 3 Jun 2012 → 7 Jun 2012 Conference number: 24

Conference

Conference	24th International Symposium on Power Semiconductor Devices and ICs
Abbreviated title	ISPSD'12
Country/Territory	Belgium
City	Bruges
Period	3/06/12 → 7/06/12

Bibliographical note

© 2012 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.

ASJC Scopus subject areas

Engineering(all)

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Experimentally validated three dimensional GCT wafer level simulations. / Lophitis, N.; Antoniou, M.; Udrea, F.; Nistor, I.; Arnold, M.; Wikström, T.; Vobecky, J.

Proceedings of the 2012 24th International Symposium on Power Semiconductor Devices and ICs, ISPSD'12. IEEE, 2012. p. 349-352 6229093.

Research output: Chapter in Book/Report/Conference proceeding › Conference proceeding › peer-review

Lophitis, N, Antoniou, M, Udrea, F, Nistor, I, Arnold, M, Wikström, T & Vobecky, J 2012, Experimentally validated three dimensional GCT wafer level simulations. in Proceedings of the 2012 24th International Symposium on Power Semiconductor Devices and ICs, ISPSD'12., 6229093, IEEE, pp. 349-352, 24th International Symposium on Power Semiconductor Devices and ICs, Bruges, Belgium, 3/06/12. https://doi.org/10.1109/ISPSD.2012.6229093

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abstract = "In this paper we present a wafer level three-dimensional simulation model of the Gate Commutated Thyristor (GCT) under inductive switching conditions. The simulations are validated by extensive experimental measurements. To the authors' knowledge such a complex simulation domain has not been used so far. This method allows the in depth study of large area devices such as GCTs, Gate Turn Off Thyristors (GTOs) and Phase Control Thyristors (PCTs). The model captures complex phenomena, such as current filamentation including subsequent failure, which allow us to predict the Maximum Controllable turn-off Current (MCC) and the Safe Operating Area (SOA) previously impossible using 2D distributed models.",

author = "N. Lophitis and M. Antoniou and F. Udrea and I. Nistor and M. Arnold and T. Wikstr{\"o}m and J. Vobecky",

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ER -

Experimentally validated three dimensional GCT wafer level simulations

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