Experimental demonstration of the p-ring FS+ Trench IGBT concept: A new design for minimizing the conduction losses

M. Antoniou; Neophytos Lophitis; F. Udrea; F. Bauer; I. Nistor; M. Bellini; M. Rahimo

doi:10.1109/ISPSD.2015.7123379

Experimental demonstration of the p-ring FS+ Trench IGBT concept: A new design for minimizing the conduction losses

M. Antoniou, Neophytos Lophitis, F. Udrea, F. Bauer, I. Nistor, M. Bellini, M. Rahimo

Research output: Contribution to conference › Paper › peer-review

18 Citations (Scopus)

Abstract

A new IGBT type structure, namely the p-ring FS+ Trench IGBT, with improved performance has been demonstrated. The improvement has been achieved through the utilization of p doped buried layers (p-rings) which allows for the simultaneous increase in the n enhancement layer doping concentration above the conventional levels without compromising the device breakdown rating. This unique lateral charge compensation approach is demonstrated to be highly effective in lowering the on-state losses. The experimental results show a 20% reduction in the on-state losses for a 1.7kV device.

Original language	English
Pages	21-24
DOIs	https://doi.org/10.1109/ISPSD.2015.7123379
Publication status	Published - 2015
Event	IEEE International Symposium on Power Semiconductor Devices and ICs (ISPSD) - , Hong Kong Duration: 10 May 2015 → 14 May 2015

Conference

Conference	IEEE International Symposium on Power Semiconductor Devices and ICs (ISPSD)
Country/Territory	Hong Kong
Period	10/05/15 → 14/05/15

Bibliographical note

The full text is currently unavailable on the repository.

Keywords

buried layers
charge compensation
insulated gate bipolar transistors
losses
IGBT type structure
conduction losses minimization design
device breakdown rating
enhancement layer doping concentration
experimental demonstration
lateral charge compensation approach
on-state losses
p doped buried layer utilization
p-ring FS+ trench IGBT concept
performance improvement
voltage 1.7 kV
Insulated Gate Bipolar Transistor (IGBT)
superjunction power MOSFET
technology trade-off
Cathodes
Doping
Electric breakdown
Insulated gate bipolar transistors
Logic gates
Performance evaluation
Switches

Access to Document

10.1109/ISPSD.2015.7123379

Cite this

Antoniou, M, Lophitis, N, Udrea, F, Bauer, F, Nistor, I, Bellini, M & Rahimo, M 2015, 'Experimental demonstration of the p-ring FS+ Trench IGBT concept: A new design for minimizing the conduction losses', Paper presented at IEEE International Symposium on Power Semiconductor Devices and ICs (ISPSD), Hong Kong, 10/05/15 - 14/05/15 pp. 21-24. https://doi.org/10.1109/ISPSD.2015.7123379

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title = "Experimental demonstration of the p-ring FS+ Trench IGBT concept: A new design for minimizing the conduction losses",

abstract = "A new IGBT type structure, namely the p-ring FS+ Trench IGBT, with improved performance has been demonstrated. The improvement has been achieved through the utilization of p doped buried layers (p-rings) which allows for the simultaneous increase in the n enhancement layer doping concentration above the conventional levels without compromising the device breakdown rating. This unique lateral charge compensation approach is demonstrated to be highly effective in lowering the on-state losses. The experimental results show a 20% reduction in the on-state losses for a 1.7kV device.",

keywords = "buried layers, charge compensation, insulated gate bipolar transistors, losses, IGBT type structure, conduction losses minimization design, device breakdown rating, enhancement layer doping concentration, experimental demonstration, lateral charge compensation approach, on-state losses, p doped buried layer utilization, p-ring FS+ trench IGBT concept, performance improvement, voltage 1.7 kV, Insulated Gate Bipolar Transistor (IGBT), superjunction power MOSFET, technology trade-off, Cathodes, Doping, Electric breakdown, Insulated gate bipolar transistors, Logic gates, Performance evaluation, Switches",

author = "M. Antoniou and Neophytos Lophitis and F. Udrea and F. Bauer and I. Nistor and M. Bellini and M. Rahimo",

note = "The full text is currently unavailable on the repository.; IEEE International Symposium on Power Semiconductor Devices and ICs (ISPSD) ; Conference date: 10-05-2015 Through 14-05-2015",

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doi = "10.1109/ISPSD.2015.7123379",

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AU - Antoniou, M.

AU - Lophitis, Neophytos

AU - Udrea, F.

AU - Bauer, F.

AU - Nistor, I.

AU - Bellini, M.

AU - Rahimo, M.

N1 - The full text is currently unavailable on the repository.

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N2 - A new IGBT type structure, namely the p-ring FS+ Trench IGBT, with improved performance has been demonstrated. The improvement has been achieved through the utilization of p doped buried layers (p-rings) which allows for the simultaneous increase in the n enhancement layer doping concentration above the conventional levels without compromising the device breakdown rating. This unique lateral charge compensation approach is demonstrated to be highly effective in lowering the on-state losses. The experimental results show a 20% reduction in the on-state losses for a 1.7kV device.

AB - A new IGBT type structure, namely the p-ring FS+ Trench IGBT, with improved performance has been demonstrated. The improvement has been achieved through the utilization of p doped buried layers (p-rings) which allows for the simultaneous increase in the n enhancement layer doping concentration above the conventional levels without compromising the device breakdown rating. This unique lateral charge compensation approach is demonstrated to be highly effective in lowering the on-state losses. The experimental results show a 20% reduction in the on-state losses for a 1.7kV device.

KW - buried layers

KW - charge compensation

KW - insulated gate bipolar transistors

KW - losses

KW - IGBT type structure

KW - conduction losses minimization design

KW - device breakdown rating

KW - enhancement layer doping concentration

KW - experimental demonstration

KW - lateral charge compensation approach

KW - on-state losses

KW - p doped buried layer utilization

KW - p-ring FS+ trench IGBT concept

KW - performance improvement

KW - voltage 1.7 kV

KW - Insulated Gate Bipolar Transistor (IGBT)

KW - superjunction power MOSFET

KW - technology trade-off

KW - Cathodes

KW - Doping

KW - Electric breakdown

KW - Insulated gate bipolar transistors

KW - Logic gates

KW - Performance evaluation

KW - Switches

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DO - 10.1109/ISPSD.2015.7123379

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T2 - IEEE International Symposium on Power Semiconductor Devices and ICs (ISPSD)

Y2 - 10 May 2015 through 14 May 2015

ER -

Experimental demonstration of the p-ring FS+ Trench IGBT concept: A new design for minimizing the conduction losses

Abstract

Conference

Bibliographical note

Keywords

Access to Document

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