Experimental and Analytical Analysis of Turn-on Parasitic Oscillation and Dynamic Current Sharing of the Si/SiC Hybrid Switch

The Si/SiC hybrid switch (HyS), consisting of a low current rated SiC MOSFET paralleled with a high current rated IGBT, can achieve high output current at low cost and reduce switching losses caused by the tail current during the IGBT turn-off transition. When the device turns on, high-frequency ringing at the gate can induce voltage overshoots and current spikes, thereby increasing the device’s current stress. The high-frequency oscillation occurs between the transistor’s capacitance and the board’s parasitic inductance. Such high-frequency oscillations also increase electromagnetic interference (EMI), which can disrupt the performance of the parallel hybrid switch. When the load current is concentrated in the MOSFET, the generated heat accelerates its degradation. Reducing the transition time needed to achieve current balancing can enhance system reliability. In this paper, a detailed turn-on analytical model has been proposed to analyze the effect of parasitic inductances and capacitances, and the current dynamic sharing transition speed to offer guidelines for Si/SiC hybrid power module design. The symmetry of the power loop inductance is also analyzed in the model, providing a more systematic and comprehensive analysis of the turn-on characteristics of the hybrid switch compared to existing models. The validity of the model is verified through simulation and experiments.