Evaluating the training dynamics of a CMOS based synapse

Arfan Ghani

doi:10.1109/IJCNN.2011.6033355

Evaluating the training dynamics of a CMOS based synapse

Arfan Ghani

Research output: Chapter in Book/Report/Conference proceeding › Conference proceeding › peer-review

3 Citations (Scopus)

Abstract

Recent work by the authors proposed compact low power synapses in hardware, based on the charge-coupling principle, that can be configured to yield a static or dynamic response. The focus of this work is to investigate the training dynamics of these synapses. Empirical models of the Post Synaptic Response (PSP), derived from hardware simulations, were developed and subsequently embedded into the MATLAB environment. A network of these synapses was then used to solve a benchmark problem using a well established training algorithm where the performance metric was convergence time, accuracy and weight range; the Spike Response Model (SRM) was used to implement point neurons. Results are presented and compared with standard synaptic responses.

Original language	English
Title of host publication	The 2011 International Joint Conference on Neural Networks (IJCNN)
Publisher	IEEE
Pages	1162-1168
Number of pages	7
ISBN (Electronic)	978-1-4244-9637-2, 978-1-4244-9636-5
ISBN (Print)	978-1-4244-9635-8
DOIs	https://doi.org/10.1109/IJCNN.2011.6033355
Publication status	Published - 2011
Event	International Joint Conference on Neural Networks - San Jose, United States Duration: 31 Jul 2011 → 5 Aug 2011

Conference

Conference	International Joint Conference on Neural Networks
Abbreviated title	IJCNN
Country/Territory	United States
City	San Jose
Period	31/07/11 → 5/08/11

Keywords

Neurons
Mathematical model
Training
Firing
Silicon
Hardware
Quations
neural nets
CMOS logic circuits
learning (artificial intelligence)
SRM
CMOS based synapse
charge-coupling principle
post synaptic response
hardware simulations
MATLAB environment
training algorithm
spike response model

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10.1109/IJCNN.2011.6033355

Cite this

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title = "Evaluating the training dynamics of a CMOS based synapse",

abstract = "Recent work by the authors proposed compact low power synapses in hardware, based on the charge-coupling principle, that can be configured to yield a static or dynamic response. The focus of this work is to investigate the training dynamics of these synapses. Empirical models of the Post Synaptic Response (PSP), derived from hardware simulations, were developed and subsequently embedded into the MATLAB environment. A network of these synapses was then used to solve a benchmark problem using a well established training algorithm where the performance metric was convergence time, accuracy and weight range; the Spike Response Model (SRM) was used to implement point neurons. Results are presented and compared with standard synaptic responses.",

keywords = "Neurons, Mathematical model, Training, Firing, Silicon, Hardware, Quations, neural nets, CMOS logic circuits, learning (artificial intelligence), SRM, CMOS based synapse, charge-coupling principle, post synaptic response, hardware simulations, MATLAB environment, training algorithm, spike response model",

author = "Arfan Ghani",

year = "2011",

doi = "10.1109/IJCNN.2011.6033355",

language = "English",

isbn = "978-1-4244-9635-8",

pages = "1162--1168",

booktitle = "The 2011 International Joint Conference on Neural Networks (IJCNN)",

publisher = "IEEE",

address = "United States",

note = "International Joint Conference on Neural Networks, IJCNN ; Conference date: 31-07-2011 Through 05-08-2011",

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PY - 2011

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AB - Recent work by the authors proposed compact low power synapses in hardware, based on the charge-coupling principle, that can be configured to yield a static or dynamic response. The focus of this work is to investigate the training dynamics of these synapses. Empirical models of the Post Synaptic Response (PSP), derived from hardware simulations, were developed and subsequently embedded into the MATLAB environment. A network of these synapses was then used to solve a benchmark problem using a well established training algorithm where the performance metric was convergence time, accuracy and weight range; the Spike Response Model (SRM) was used to implement point neurons. Results are presented and compared with standard synaptic responses.

KW - Neurons

KW - Mathematical model

KW - Training

KW - Firing

KW - Silicon

KW - Hardware

KW - Quations

KW - neural nets

KW - CMOS logic circuits

KW - learning (artificial intelligence)

KW - SRM

KW - CMOS based synapse

KW - charge-coupling principle

KW - post synaptic response

KW - hardware simulations

KW - MATLAB environment

KW - training algorithm

KW - spike response model

U2 - 10.1109/IJCNN.2011.6033355

DO - 10.1109/IJCNN.2011.6033355

M3 - Conference proceeding

SN - 978-1-4244-9635-8

SP - 1162

EP - 1168

BT - The 2011 International Joint Conference on Neural Networks (IJCNN)

PB - IEEE

T2 - International Joint Conference on Neural Networks

Y2 - 31 July 2011 through 5 August 2011

ER -

Evaluating the training dynamics of a CMOS based synapse

Abstract

Conference

Keywords

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