Evaluating the training dynamics of a CMOS based synapse

Arfan Ghani

Research output: Chapter in Book/Report/Conference proceedingConference proceedingpeer-review

3 Citations (Scopus)


Recent work by the authors proposed compact low power synapses in hardware, based on the charge-coupling principle, that can be configured to yield a static or dynamic response. The focus of this work is to investigate the training dynamics of these synapses. Empirical models of the Post Synaptic Response (PSP), derived from hardware simulations, were developed and subsequently embedded into the MATLAB environment. A network of these synapses was then used to solve a benchmark problem using a well established training algorithm where the performance metric was convergence time, accuracy and weight range; the Spike Response Model (SRM) was used to implement point neurons. Results are presented and compared with standard synaptic responses.
Original languageEnglish
Title of host publicationThe 2011 International Joint Conference on Neural Networks (IJCNN)
Number of pages7
ISBN (Electronic)978-1-4244-9637-2, 978-1-4244-9636-5
ISBN (Print)978-1-4244-9635-8
Publication statusPublished - 2011
EventInternational Joint Conference on Neural Networks - San Jose, United States
Duration: 31 Jul 20115 Aug 2011


ConferenceInternational Joint Conference on Neural Networks
Abbreviated titleIJCNN
Country/TerritoryUnited States
CitySan Jose


  • Neurons
  • Mathematical model
  • Training
  • Firing
  • Silicon
  • Hardware
  • Quations
  • neural nets
  • CMOS logic circuits
  • learning (artificial intelligence)
  • SRM
  • CMOS based synapse
  • charge-coupling principle
  • post synaptic response
  • hardware simulations
  • MATLAB environment
  • training algorithm
  • spike response model


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