Evaluating the generalisation capability of a CMOS based synapse

A. Ghani, L. McDaid, A. Belatreche, S. Hall, S. Huang, J. Marsland, T. Dowrick, A. Smith

Research output: Contribution to journalArticle

3 Citations (Scopus)

Abstract

The focus of this work is to investigate the generalisation capability of compact, solid-state synapses recently proposed by the authors. The synapses can be configured to yield a static or dynamic response. Empirical models of the Post Synaptic Response (PSP), derived from hardware simulations, are developed and embedded into the neural network toolbox in MATLAB. A network of these synapses was then used to solve benchmark problems using a well-established training algorithm where the performance metric was convergence time, accuracy and weight range; the Spike Response Model (SRM) was used to implement point neurons. Results are presented and compared with standard synaptic responses.

Original languageEnglish
Pages (from-to)188-197
Number of pages10
JournalNeurocomputing
Volume83
DOIs
Publication statusPublished - 15 Apr 2012
Externally publishedYes

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Keywords

  • CMOS implementation of spiking neurons
  • CMOS synapses
  • Spiking neural networks

ASJC Scopus subject areas

  • Computer Science Applications
  • Cognitive Neuroscience
  • Artificial Intelligence

Cite this

Ghani, A., McDaid, L., Belatreche, A., Hall, S., Huang, S., Marsland, J., ... Smith, A. (2012). Evaluating the generalisation capability of a CMOS based synapse. Neurocomputing, 83, 188-197. https://doi.org/10.1016/j.neucom.2011.12.010