Deep p-ring trench termination: An innovative and cost-effective way to reduce silicon area

Marina Antoniou; Neophytos Lophitis; Florin Udrea; Munaf T. Rahimo; Umamaheswara Reddy Vemulapati; Ciara Corvarsce; Uwe Badstuebner

doi:10.1109/LED.2018.2890702

Deep p-ring trench termination: An innovative and cost-effective way to reduce silicon area

Marina Antoniou, Neophytos Lophitis, Florin Udrea, Munaf T. Rahimo, Umamaheswara Reddy Vemulapati, Ciara Corvarsce, Uwe Badstuebner

Research output: Contribution to journal › Article › peer-review

5 Citations (Scopus)

90 Downloads (Pure)

Abstract

A new type of high-voltage termination, namely the 'deep p-ring trench' termination design for high-voltage, high-power devices, is presented and extensively simulated. Termination of such devices consumes a large proportion of the chip size; the proposed design concept not only reduces the termination silicon area required but also removes the need for an additional mask as is the case of the traditional p+ ring-type termination. Furthermore, the presence of the p-ring under and around the bottom of the trench structure reduces the electric field peaks at the corners of the oxide, which results in reduced hot carrier injection and improved device reliability.

Original language	English
Pages (from-to)	177 - 180
Number of pages	4
Journal	IEEE Electron Device Letters
Volume	40
Issue number	2
Early online date	3 Jan 2019
DOIs	https://doi.org/10.1109/LED.2018.2890702
Publication status	Published - Feb 2019

Bibliographical note

© 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.

Copyright © and Moral Rights are retained by the author(s) and/ or other copyright owners. A copy can be downloaded for personal non-commercial research or study, without prior permission or charge. This item cannot be reproduced or quoted extensively from without first obtaining permission in writing from the copyright holder(s). The content must not be changed in any way or sold commercially in any format or medium without the formal permission of the copyright holders.

Keywords

high voltage
Power semiconductor devices
termination

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Access to Document

10.1109/LED.2018.2890702

Post-PrintAccepted author manuscript, 1.14 MB

Cite this

@article{af8abd018de34b38bc19daca4a571b29,

title = "Deep p-ring trench termination: An innovative and cost-effective way to reduce silicon area",

abstract = "A new type of high-voltage termination, namely the 'deep p-ring trench' termination design for high-voltage, high-power devices, is presented and extensively simulated. Termination of such devices consumes a large proportion of the chip size; the proposed design concept not only reduces the termination silicon area required but also removes the need for an additional mask as is the case of the traditional p+ ring-type termination. Furthermore, the presence of the p-ring under and around the bottom of the trench structure reduces the electric field peaks at the corners of the oxide, which results in reduced hot carrier injection and improved device reliability.",

keywords = "high voltage, Power semiconductor devices, termination",

author = "Marina Antoniou and Neophytos Lophitis and Florin Udrea and Rahimo, {Munaf T.} and Vemulapati, {Umamaheswara Reddy} and Ciara Corvarsce and Uwe Badstuebner",

note = "{\textcopyright} 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. Copyright {\textcopyright} and Moral Rights are retained by the author(s) and/ or other copyright owners. A copy can be downloaded for personal non-commercial research or study, without prior permission or charge. This item cannot be reproduced or quoted extensively from without first obtaining permission in writing from the copyright holder(s). The content must not be changed in any way or sold commercially in any format or medium without the formal permission of the copyright holders. ",

year = "2019",

month = feb,

doi = "10.1109/LED.2018.2890702",

language = "English",

volume = "40",

pages = "177 -- 180",

journal = "IEEE Electron Device Letters",

issn = "0741-3106",

publisher = "Institute of Electrical and Electronics Engineers",

number = "2",

}

TY - JOUR

T1 - Deep p-ring trench termination

T2 - An innovative and cost-effective way to reduce silicon area

AU - Antoniou, Marina

AU - Lophitis, Neophytos

AU - Udrea, Florin

AU - Rahimo, Munaf T.

AU - Vemulapati, Umamaheswara Reddy

AU - Corvarsce, Ciara

AU - Badstuebner, Uwe

N1 - © 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. Copyright © and Moral Rights are retained by the author(s) and/ or other copyright owners. A copy can be downloaded for personal non-commercial research or study, without prior permission or charge. This item cannot be reproduced or quoted extensively from without first obtaining permission in writing from the copyright holder(s). The content must not be changed in any way or sold commercially in any format or medium without the formal permission of the copyright holders.

PY - 2019/2

Y1 - 2019/2

N2 - A new type of high-voltage termination, namely the 'deep p-ring trench' termination design for high-voltage, high-power devices, is presented and extensively simulated. Termination of such devices consumes a large proportion of the chip size; the proposed design concept not only reduces the termination silicon area required but also removes the need for an additional mask as is the case of the traditional p+ ring-type termination. Furthermore, the presence of the p-ring under and around the bottom of the trench structure reduces the electric field peaks at the corners of the oxide, which results in reduced hot carrier injection and improved device reliability.

AB - A new type of high-voltage termination, namely the 'deep p-ring trench' termination design for high-voltage, high-power devices, is presented and extensively simulated. Termination of such devices consumes a large proportion of the chip size; the proposed design concept not only reduces the termination silicon area required but also removes the need for an additional mask as is the case of the traditional p+ ring-type termination. Furthermore, the presence of the p-ring under and around the bottom of the trench structure reduces the electric field peaks at the corners of the oxide, which results in reduced hot carrier injection and improved device reliability.

KW - high voltage

KW - Power semiconductor devices

KW - termination

UR - http://www.scopus.com/inward/record.url?scp=85061077887&partnerID=8YFLogxK

U2 - 10.1109/LED.2018.2890702

DO - 10.1109/LED.2018.2890702

M3 - Article

SN - 0741-3106

VL - 40

SP - 177

EP - 180

JO - IEEE Electron Device Letters

JF - IEEE Electron Device Letters

IS - 2

ER -

Deep p-ring trench termination: An innovative and cost-effective way to reduce silicon area

Abstract

Bibliographical note

Keywords

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this