Comparative Analysis of Transient Characteristics of Gate Driver Topologies in Paralleled Silicon Carbide Power Modules

Due to the extremely fast switching speed and low on‐resistance of silicon carbide (SiC) MOSFETs, their parallel interconnection is prone to current imbalance caused by mismatched parasitic parameters and inconsistent gate signals in the parallel branches. Especially for paralleled structures consisting of multiple high‐power SiC power modules, achieving a symmetrical, parameter‐matched circuit design is challenging due to constraints such as heat dissipation and spatial limitations. Furthermore, increased spacing between parallel modules increases parasitic inductance in the power loop as well as the gate drive loop, potentially inducing gate voltage oscillations. Thus, ensuring current sharing and operational stability in multi‐module paralleled structures remain critical challenges. In this article, the current sharing principle of paralleled SiC devices is analysed, and a symmetrical DC/AC busbar structure is proposed for three parallel 1200 V/300 A SiC modules to achieve current balancing during conduction. Based on this structure, the transient current sharing of three gate driver topologies is compared, and the gate voltage oscillation principle affecting operational stability is analysed. Finally, the applicability of these gate driver topologies for multi‐device parallel structures is evaluated, and a hardware solution is summarised to facilitate current sharing and stable operation of parallel SiC MOSFET modules.