Area efficient architecture for large scale implementation of biologically plausible spiking neural networks on reconfigurable hardware

Arfan Ghani; T. M. McGinnity; Liam Maguire; Jim Harkin

doi:10.1109/FPL.2006.311352

Area efficient architecture for large scale implementation of biologically plausible spiking neural networks on reconfigurable hardware

Arfan Ghani, T. M. McGinnity, Liam Maguire, Jim Harkin

Research output: Chapter in Book/Report/Conference proceeding › Conference proceeding › peer-review

15 Citations (Scopus)

Abstract

In this paper an area efficient multiplier-less hardware architecture is proposed for the implementation of an integrate- and-fire SNN model. The proposed architecture is intended for large scale implementation on a single FPGA. A modular design is proposed in order to make it flexible. Synaptic multiplication is performed with a simple AND gate, and pulses from different synapses are added together at different times, replicating the accumulation of synaptic inputs for the membrane potential. In order to introduce non-linearity into the membrane potential a normalized random number is introduced to this state variable. The proposed architecture uses spike trains as an input much like those in real networks

Original language	English
Title of host publication	IEEE International Conference on Field Programmable Logic and Applications
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	1-2
Number of pages	2
ISBN (Print)	1-4244-0312-X
DOIs	https://doi.org/10.1109/FPL.2006.311352
Publication status	Published - 2006
Event	IEEE International Conference on Field Programmable Logic and Applications - Madrid, Spain Duration: 28 Aug 2006 → 30 Aug 2006

Conference

Conference	IEEE International Conference on Field Programmable Logic and Applications
Country/Territory	Spain
City	Madrid
Period	28/08/06 → 30/08/06

Keywords

Large-scale systems
Neural networks
Neural network hardware
Neurons
Biomembranes,
Fires
Humans
Computer architecture
Biological neural networks
Systems engineering and theory

Access to Document

10.1109/FPL.2006.311352

Cite this

Ghani, A., McGinnity, T. M., Maguire, L., & Harkin, J. (2006). Area efficient architecture for large scale implementation of biologically plausible spiking neural networks on reconfigurable hardware. In IEEE International Conference on Field Programmable Logic and Applications (pp. 1-2). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/FPL.2006.311352

Area efficient architecture for large scale implementation of biologically plausible spiking neural networks on reconfigurable hardware. / Ghani, Arfan; McGinnity, T. M.; Maguire, Liam et al.
IEEE International Conference on Field Programmable Logic and Applications. Institute of Electrical and Electronics Engineers Inc., 2006. p. 1-2.

Research output: Chapter in Book/Report/Conference proceeding › Conference proceeding › peer-review

Ghani, A, McGinnity, TM, Maguire, L & Harkin, J 2006, Area efficient architecture for large scale implementation of biologically plausible spiking neural networks on reconfigurable hardware. in IEEE International Conference on Field Programmable Logic and Applications. Institute of Electrical and Electronics Engineers Inc., pp. 1-2, IEEE International Conference on Field Programmable Logic and Applications, Madrid, Spain, 28/08/06. https://doi.org/10.1109/FPL.2006.311352

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title = "Area efficient architecture for large scale implementation of biologically plausible spiking neural networks on reconfigurable hardware",

abstract = "In this paper an area efficient multiplier-less hardware architecture is proposed for the implementation of an integrate- and-fire SNN model. The proposed architecture is intended for large scale implementation on a single FPGA. A modular design is proposed in order to make it flexible. Synaptic multiplication is performed with a simple AND gate, and pulses from different synapses are added together at different times, replicating the accumulation of synaptic inputs for the membrane potential. In order to introduce non-linearity into the membrane potential a normalized random number is introduced to this state variable. The proposed architecture uses spike trains as an input much like those in real networks",

keywords = "Large-scale systems, Neural networks, Neural network hardware, Neurons, Biomembranes,, Fires, Humans, Computer architecture, Biological neural networks, Systems engineering and theory",

author = "Arfan Ghani and McGinnity, {T. M.} and Liam Maguire and Jim Harkin",

year = "2006",

doi = "10.1109/FPL.2006.311352",

language = "English",

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booktitle = "IEEE International Conference on Field Programmable Logic and Applications",

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AB - In this paper an area efficient multiplier-less hardware architecture is proposed for the implementation of an integrate- and-fire SNN model. The proposed architecture is intended for large scale implementation on a single FPGA. A modular design is proposed in order to make it flexible. Synaptic multiplication is performed with a simple AND gate, and pulses from different synapses are added together at different times, replicating the accumulation of synaptic inputs for the membrane potential. In order to introduce non-linearity into the membrane potential a normalized random number is introduced to this state variable. The proposed architecture uses spike trains as an input much like those in real networks

KW - Large-scale systems

KW - Neural networks

KW - Neural network hardware

KW - Neurons

KW - Biomembranes,

KW - Fires

KW - Humans

KW - Computer architecture

KW - Biological neural networks

KW - Systems engineering and theory

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M3 - Conference proceeding

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EP - 2

BT - IEEE International Conference on Field Programmable Logic and Applications

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - IEEE International Conference on Field Programmable Logic and Applications

Y2 - 28 August 2006 through 30 August 2006

ER -

Area efficient architecture for large scale implementation of biologically plausible spiking neural networks on reconfigurable hardware

Abstract

Conference

Keywords

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