Area efficient architecture for large scale implementation of biologically plausible spiking neural networks on reconfigurable hardware

Arfan Ghani, T. M. McGinnity, Liam Maguire, Jim Harkin

Research output: Chapter in Book/Report/Conference proceedingConference proceeding

5 Citations (Scopus)

Abstract

In this paper an area efficient multiplier-less hardware architecture is proposed for the implementation of an integrate- and-fire SNN model. The proposed architecture is intended for large scale implementation on a single FPGA. A modular design is proposed in order to make it flexible. Synaptic multiplication is performed with a simple AND gate, and pulses from different synapses are added together at different times, replicating the accumulation of synaptic inputs for the membrane potential. In order to introduce non-linearity into the membrane potential a normalized random number is introduced to this state variable. The proposed architecture uses spike trains as an input much like those in real networks
Original languageEnglish
Title of host publicationIEEE International Conference on Field Programmable Logic and Applications
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1-2
Number of pages2
ISBN (Print)1-4244-0312-X
DOIs
Publication statusPublished - 2006
EventIEEE International Conference on Field Programmable Logic and Applications - Madrid, Spain
Duration: 28 Aug 200630 Aug 2006

Conference

ConferenceIEEE International Conference on Field Programmable Logic and Applications
CountrySpain
CityMadrid
Period28/08/0630/08/06

Keywords

  • Large-scale systems
  • Neural networks
  • Neural network hardware
  • Neurons
  • Biomembranes,
  • Fires
  • Humans
  • Computer architecture
  • Biological neural networks
  • Systems engineering and theory

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    Ghani, A., McGinnity, T. M., Maguire, L., & Harkin, J. (2006). Area efficient architecture for large scale implementation of biologically plausible spiking neural networks on reconfigurable hardware. In IEEE International Conference on Field Programmable Logic and Applications (pp. 1-2). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/FPL.2006.311352