Abstract
Original language | English |
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Pages (from-to) | 2900 - 2905 |
Number of pages | 6 |
Journal | IEEE Transactions on Electron Devices |
Volume | 64 |
Issue number | 7 |
DOIs | |
Publication status | Published - 18 May 2017 |
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Keywords
- Compact model
- current collapse (CC)
- double-pulse switch
- drain-lag
- GaN HEMTs
- gate-lag
- switching transients
- technology computer-aided design (TCAD)
Cite this
Analysis of GaN HEMTs Switching Transients Using Compact Model. / Faramehr, Soroush; Igic, Petar.
In: IEEE Transactions on Electron Devices, Vol. 64, No. 7, 18.05.2017, p. 2900 - 2905.Research output: Contribution to journal › Article
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TY - JOUR
T1 - Analysis of GaN HEMTs Switching Transients Using Compact Model
AU - Faramehr, Soroush
AU - Igic, Petar
PY - 2017/5/18
Y1 - 2017/5/18
N2 - This paper presents a methodology to model GaN power HEMT switching transients. Thus, a compact model to predict devices' pulse switching characteristics and current collapse reliability issue has been developed. Parasitic RC subcircuits and a standard double-pulse switching tester to model intrinsic parasitic effects and to analyze power dissipation of GaN power HEMT are proposed and presented. Switching transient including gate-lag and drain-lag is predicted for ideal (without trap) and nonideal (with trap) devices. The results are validated by and compared to 2-D finite-element technology computer-aided design simulations. The original aim of this exercise is to develop a fast (near-real-time) model which can predict dynamic behavior of single and multiple power GaN HEMTs used for the switching transients of GaN power devices at circuit level.
AB - This paper presents a methodology to model GaN power HEMT switching transients. Thus, a compact model to predict devices' pulse switching characteristics and current collapse reliability issue has been developed. Parasitic RC subcircuits and a standard double-pulse switching tester to model intrinsic parasitic effects and to analyze power dissipation of GaN power HEMT are proposed and presented. Switching transient including gate-lag and drain-lag is predicted for ideal (without trap) and nonideal (with trap) devices. The results are validated by and compared to 2-D finite-element technology computer-aided design simulations. The original aim of this exercise is to develop a fast (near-real-time) model which can predict dynamic behavior of single and multiple power GaN HEMTs used for the switching transients of GaN power devices at circuit level.
KW - Compact model
KW - current collapse (CC)
KW - double-pulse switch
KW - drain-lag
KW - GaN HEMTs
KW - gate-lag
KW - switching transients
KW - technology computer-aided design (TCAD)
U2 - 10.1109/TED.2017.2703103
DO - 10.1109/TED.2017.2703103
M3 - Article
VL - 64
SP - 2900
EP - 2905
JO - IEEE Transactions on Electron Devices
JF - IEEE Transactions on Electron Devices
SN - 0018-9383
IS - 7
ER -