Abstract
This paper describes recent experimental work carried on the optimisation of junction isolation structures for use in Power Integrated Circuits. Isolation is required to collect minority carriers injected into the substrate before the can reach the low voltage control circuitry. The most effect form of isolation found in this paper combines A number of techniques (SJI & MAAP) to reduce the injected current by3 orders of magnitude compared with the standard junction isolation techniques.
Original language | English |
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Title of host publication | 2004 24th International Conference on Microelectronics (IEEE Cat. No.04TH8716) |
Publisher | IEEE |
Pages | 17-22 |
Number of pages | 6 |
Volume | 1 |
ISBN (Print) | 0-7803-8166-1 |
DOIs | |
Publication status | Published - 19 Jul 2004 |
Event | 2004 24th International Conference on Microelectronics - Nis, Serbia, Nis, Serbia Duration: 16 May 2004 → 19 May 2004 Conference number: 24 |
Conference
Conference | 2004 24th International Conference on Microelectronics |
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Abbreviated title | MIEL 2004 |
Country/Territory | Serbia |
City | Nis |
Period | 16/05/04 → 19/05/04 |
Keywords
- Power integrated circuits
- Integrated circuit technology
- Isolation technology
- Protection
- Dielectric substrates
- Low voltage
- Silicon on insulator technology
- CMOS technology
- Power transistors
- Dielectric devices
ASJC Scopus subject areas
- Engineering(all)