Advanced junction isolation structures for Power Integrated Circuit technology

P. A. Mawby, T. K.H. Starke, P. M. Holland, S. Hussain, W. M. Jamal, P. M. Igic

    Research output: Chapter in Book/Report/Conference proceedingConference proceedingpeer-review

    Abstract

    This paper describes recent experimental work carried on the optimisation of junction isolation structures for use in Power Integrated Circuits. Isolation is required to collect minority carriers injected into the substrate before the can reach the low voltage control circuitry. The most effect form of isolation found in this paper combines A number of techniques (SJI & MAAP) to reduce the injected current by3 orders of magnitude compared with the standard junction isolation techniques.
    Original languageEnglish
    Title of host publication2004 24th International Conference on Microelectronics (IEEE Cat. No.04TH8716)
    PublisherIEEE
    Pages17-22
    Number of pages6
    Volume1
    ISBN (Print)0-7803-8166-1
    DOIs
    Publication statusPublished - 19 Jul 2004
    Event2004 24th International Conference on Microelectronics - Nis, Serbia, Nis, Serbia
    Duration: 16 May 200419 May 2004
    Conference number: 24

    Conference

    Conference2004 24th International Conference on Microelectronics
    Abbreviated titleMIEL 2004
    Country/TerritorySerbia
    CityNis
    Period16/05/0419/05/04

    Keywords

    • Power integrated circuits
    • Integrated circuit technology
    • Isolation technology
    • Protection
    • Dielectric substrates
    • Low voltage
    • Silicon on insulator technology
    • CMOS technology
    • Power transistors
    • Dielectric devices

    ASJC Scopus subject areas

    • Engineering(all)

    Fingerprint

    Dive into the research topics of 'Advanced junction isolation structures for Power Integrated Circuit technology'. Together they form a unique fingerprint.

    Cite this