Acceleration of Polynomial Matrix Multiplication on Zynq-7000 System-on-Chip

S. Kasap; S. Redif; E. W. Wachter

doi:10.1109/socc46988.2019.1570555424

Acceleration of Polynomial Matrix Multiplication on Zynq-7000 System-on-Chip

S. Kasap, S. Redif, E. W. Wachter

Research output: Chapter in Book/Report/Conference proceeding › Conference proceeding › peer-review

1 Citation (Scopus)

Abstract

In this paper, we propose a second-generation hardware solution which boasts more versatility, efficiency and scalability compared to our previous design. This is achieved through the design of a highly versatile PMM accelerator which supports polynomial matrices of any size, as a component of the embedded system developed within the Xilinx Zynq-7000 AP SoC. Experimental results demonstrate the efficiency and effectiveness of our novel SoC-based PMM accelerator in the context of a generic problem, where a maximum speed-up of ≈ 67× is accomplished, without compromising the accuracy.

Original language	English
Title of host publication	2019 32nd IEEE International System-on-Chip Conference (SOCC)
Pages	300-305
Number of pages	6
ISBN (Electronic)	978-1-7281-3483-3
DOIs	https://doi.org/10.1109/socc46988.2019.1570555424
Publication status	Published - Sept 2019
Externally published	Yes
Event	2019 32nd IEEE International System-on-Chip Conference - Singapore, Singapore Duration: 3 Sept 2019 → 6 Sept 2019 Conference number: 32 http://socc2019.ieee-socc.org/

Conference

Conference	2019 32nd IEEE International System-on-Chip Conference
Abbreviated title	SOCC
Country/Territory	Singapore
City	Singapore
Period	3/09/19 → 6/09/19
Internet address	http://socc2019.ieee-socc.org/

Keywords

Polynomial Matrix Multiplication
Hardware/Software Co-Design
Zynq-7000 AP SoC

Access to Document

10.1109/socc46988.2019.1570555424

Cite this

@inproceedings{869c46b402994a82a8a2afc42560a327,

title = "Acceleration of Polynomial Matrix Multiplication on Zynq-7000 System-on-Chip",

abstract = "In this paper, we propose a second-generation hardware solution which boasts more versatility, efficiency and scalability compared to our previous design. This is achieved through the design of a highly versatile PMM accelerator which supports polynomial matrices of any size, as a component of the embedded system developed within the Xilinx Zynq-7000 AP SoC. Experimental results demonstrate the efficiency and effectiveness of our novel SoC-based PMM accelerator in the context of a generic problem, where a maximum speed-up of ≈ 67× is accomplished, without compromising the accuracy.",

keywords = "Polynomial Matrix Multiplication, Hardware/Software Co-Design, Zynq-7000 AP SoC",

author = "S. Kasap and S. Redif and Wachter, \{E. W.\}",

year = "2019",

month = sep,

doi = "10.1109/socc46988.2019.1570555424",

language = "English",

pages = "300--305",

booktitle = "2019 32nd IEEE International System-on-Chip Conference (SOCC)",

note = "2019 32nd IEEE International System-on-Chip Conference, SOCC ; Conference date: 03-09-2019 Through 06-09-2019",

url = "http://socc2019.ieee-socc.org/",

}

TY - GEN

T1 - Acceleration of Polynomial Matrix Multiplication on Zynq-7000 System-on-Chip

AU - Kasap, S.

AU - Redif, S.

AU - Wachter, E. W.

N1 - Conference code: 32

PY - 2019/9

Y1 - 2019/9

N2 - In this paper, we propose a second-generation hardware solution which boasts more versatility, efficiency and scalability compared to our previous design. This is achieved through the design of a highly versatile PMM accelerator which supports polynomial matrices of any size, as a component of the embedded system developed within the Xilinx Zynq-7000 AP SoC. Experimental results demonstrate the efficiency and effectiveness of our novel SoC-based PMM accelerator in the context of a generic problem, where a maximum speed-up of ≈ 67× is accomplished, without compromising the accuracy.

AB - In this paper, we propose a second-generation hardware solution which boasts more versatility, efficiency and scalability compared to our previous design. This is achieved through the design of a highly versatile PMM accelerator which supports polynomial matrices of any size, as a component of the embedded system developed within the Xilinx Zynq-7000 AP SoC. Experimental results demonstrate the efficiency and effectiveness of our novel SoC-based PMM accelerator in the context of a generic problem, where a maximum speed-up of ≈ 67× is accomplished, without compromising the accuracy.

KW - Polynomial Matrix Multiplication

KW - Hardware/Software Co-Design

KW - Zynq-7000 AP SoC

UR - http://dx.doi.org/10.1109/socc46988.2019.1570555424

UR - https://www.scopus.com/pages/publications/85085174528

U2 - 10.1109/socc46988.2019.1570555424

DO - 10.1109/socc46988.2019.1570555424

M3 - Conference proceeding

SP - 300

EP - 305

BT - 2019 32nd IEEE International System-on-Chip Conference (SOCC)

T2 - 2019 32nd IEEE International System-on-Chip Conference

Y2 - 3 September 2019 through 6 September 2019

ER -

Acceleration of Polynomial Matrix Multiplication on Zynq-7000 System-on-Chip

Abstract

Conference

Keywords

Access to Document

Other files and links

Fingerprint

Cite this