A new hardware approach to self-organizing maps

Leonardo A. Dias, Maria G.F. Coutinho, Elena Gaura, Marcelo A.C. Fernandes

Research output: Chapter in Book/Report/Conference proceedingConference proceedingpeer-review

Abstract

Self-Organizing Maps (SOMs) are widely used as a data mining technique for applications that require data dimensionality reduction and clustering. Given the complexity of the SOM learning phase and the massive dimensionality of many data sets as well as their sample size in Big Data applications, high-speed processing is critical when implementing SOM approaches. This paper proposes a new hardware approach to SOM implementation, exploiting parallelization, to optimize the system's processing time. Unlike most implementations in the literature, this proposed approach allows the parallelization of the data dimensions instead of the map, ensuring high processing speed regardless of data dimensions. An implementation with field-programmable gate arrays (FPGA) is presented and evaluated. Key evaluation metrics are processing time (or throughput) and FPGA area occupancy (or hardware resources).

Original languageEnglish
Title of host publicationProceedings - 2020 IEEE 31st International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2020
EditorsFrank Hannig, Javier Navaridas, Dirk Koch, Ameer Abdelhadi
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages205-212
Number of pages8
ISBN (Electronic)9781728171470
DOIs
Publication statusPublished - 31 Jul 2020
Event31st IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2020 - Manchester, United Kingdom
Duration: 6 Jul 20208 Jul 2020

Publication series

NameProceedings of the International Conference on Application-Specific Systems, Architectures and Processors
Volume2020-July
ISSN (Print)1063-6862

Conference

Conference31st IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2020
CountryUnited Kingdom
CityManchester
Period6/07/208/07/20

Keywords

  • Big Data
  • FPGA
  • Hardware
  • Self-Organizing Map

ASJC Scopus subject areas

  • Hardware and Architecture
  • Computer Networks and Communications

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