@inproceedings{5d1f5e9461a14533a7080747b9a09ebf,
title = "A new hardware approach to self-organizing maps",
abstract = "Self-Organizing Maps (SOMs) are widely used as a data mining technique for applications that require data dimensionality reduction and clustering. Given the complexity of the SOM learning phase and the massive dimensionality of many data sets as well as their sample size in Big Data applications, high-speed processing is critical when implementing SOM approaches. This paper proposes a new hardware approach to SOM implementation, exploiting parallelization, to optimize the system's processing time. Unlike most implementations in the literature, this proposed approach allows the parallelization of the data dimensions instead of the map, ensuring high processing speed regardless of data dimensions. An implementation with field-programmable gate arrays (FPGA) is presented and evaluated. Key evaluation metrics are processing time (or throughput) and FPGA area occupancy (or hardware resources). ",
keywords = "Big Data, FPGA, Hardware, Self-Organizing Map",
author = "Dias, {Leonardo A.} and Coutinho, {Maria G.F.} and Elena Gaura and Fernandes, {Marcelo A.C.}",
year = "2020",
month = jul,
day = "31",
doi = "10.1109/ASAP49362.2020.00041",
language = "English",
series = "Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "205--212",
editor = "Frank Hannig and Javier Navaridas and Dirk Koch and Ameer Abdelhadi",
booktitle = "Proceedings - 2020 IEEE 31st International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2020",
address = "United States",
note = "31st IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2020 ; Conference date: 06-07-2020 Through 08-07-2020",
}