A Defects’ based model on the Barrier Height behaviour in 3C-SiC-on-Si Schottky Barrier Diodes

3C-Silicon Carbide (3C-SiC) Schottky Barrier Diodes on Silicon (Si) substrates (3C-SiC-on-Si) have been found to suffer of excessive sub-threshold current, despite the superior electrical properties of 3C-SiC. In turn, that is one of the factors deterring the commercialization of this technology. The forward Current-Voltage (I-V) characteristics in these devices carry considerable information about the material quality. In this context, an advanced Technology Computer Aided Design (TCAD) model is proposed and validated with measurements obtained from a fabricated and characterized Platinum/3C-SiC-on-Si Schottky Barrier Diode with scope to shed light in the physical carrier transport mechanisms, the impact of traps and their characteristics on the actual device performance. The model includes defects originating from both the Schottky contact and the hetero-interface of 3C-SiC with Si, which allows the investigation of their impact on the magnification of the sub-threshold current. Further, the simulation results and measured data allowed for the identification of additional distributions of interfacial states, the effect of which is linked to the observed non-uniformities of the Barrier Height value. A comprehensive characterization of the defects affecting the carrier transport mechanisms of the investigated 3C-SiC-on-Si power diode is thus achieved and the proposed TCAD model is able to accurately predict the device current both during forward and reverse bias conditions.